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ORCIDDebashis Bhattacharya
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2000 – 2009
- 2005
[j8]Rob Roy, Debashis Bhattacharya, Vamsi Boppana:
Transistor-Level Optimization of Digital Designs with Flex Cells. Computer 38(2): 53-61 (2005)
1990 – 1999
- 1999
- [c13]Debashis Bhattacharya:
Instruction-Driven Wake-Up Mechanisms for Snoopy TAP Controller. VTS 1999: 467-472 - 1998
- [c12]Debashis Bhattacharya:
Hierarchical Test Access Architecture for Embedded Cores in an Integrated Circuit. VTS 1998: 8-14 - 1997
- [j7]Debashis Bhattacharya, Satyabroto Sinha:
Invariance of stereo images via the theory of complex moments. Pattern Recognit. 30(9): 1373-1386 (1997) - [c11]Naushik Sankarayya, Kaushik Roy, Debashis Bhattacharya:
Optimizing computations in a transposed direct form realization of floating-point LTI-FIR systems. ICCAD 1997: 120-125 - [c10]Naushik Sankarayya, Kaushik Roy, Debashis Bhattacharya:
Algorithms for Low Power FIR Filter Realization Using Differential Coefficients. VLSI Design 1997: 174-178 - [c9]Debashis Bhattacharya, Smith Freeman, Bill Lin:
Optimizing Test Hardware for At-Speed Testing of Datapaths in an Integrated Circuit. VLSI Design 1997: 289-296 - 1995
- [j6]Shang-E Tai, Debashis Bhattacharya:
A three-stage partial scan design method to ease ATPG. J. Electron. Test. 7(1-2): 95-104 (1995) - [j5]Debashis Bhattacharya, Prathima Agrawal, Vishwani D. Agrawal:
Test Generation for Path Delay Faults Using Binary Decision Diagrams. IEEE Trans. Computers 44(3): 434-447 (1995) - [j4]Ted Stanion, Debashis Bhattacharya, Carl Sechen:
An efficient method for generating exhaustive test sets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(12): 1516-1525 (1995) - 1994
- [c8]Shang-E Tai, Debashis Bhattacharya:
A Three-Stage Partial Scan Design Method Using the Sequential Circuit Flow Graph. VLSI Design 1994: 101-106 - 1993
- [c7]Debashis Bhattacharya, Prathima Agrawal:
Boolean algebraic test generation using a distributed system. ICCAD 1993: 440-443 - [c6]Shang-E Tai, Debashis Bhattacharya:
Pipelined Fault Simulation on Parallel Machines Using the Circuit Flow Graph. ICCD 1993: 564-567 - [c5]Kumar N. Lalgudi, Debashis Bhattacharya, Prathima Agrawal:
Architecture of a Min-Max Simulator on MARS. VLSI Design 1993: 246-249 - 1992
- [c4]Debashis Bhattacharya, Prathima Agrawal, Vishwani D. Agrawal:
Delay Fault Test Generation for Scan/Hold Circuits Using Boolean Expressions. DAC 1992: 159-164 - 1991
- [c3]Ted Stanion, Debashis Bhattacharya:
TSUNAMI: A Path Oriented Scheme for Algebraic Test Generation. FTCS 1991: 36-43 - 1990
- [j3]Debashis Bhattacharya, John P. Hayes:
A hierarchical test generation methodology for digital circuits. J. Electron. Test. 1(2): 103-123 (1990) - [j2]Debashis Bhattacharya, John P. Hayes:
Designing for high-level test generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(7): 752-766 (1990) - [c2]Debashis Bhattacharya:
Binary to Quaternary Encoding in Clocked CMOS Circuits Using Weak Buffer. ISMVL 1990: 174-180 - [c1]Ajit Agrawal, Debashis Bhattacharya:
CMP3F: a high speed fault simulator for the Connection Machine. ITC 1990: 410-416
1980 – 1989
- 1989
- [j1]Debashis Bhattacharya, Brian T. Murray, John P. Hayes:
High-Level Test Generation for VLSI. Computer 22(4): 16-24 (1989) - 1988
- [b1]Debashis Bhattacharya:
Hierarchical modeling and test generation for digital circuits. University of Michigan, USA, 1988
Coauthor Index
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