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2020 – today
- 2024
[c13]Rie Kometani, Shinobu Nagayama, Martin Lukac, Masato Inagi, Shin'ichi Wakabayashi:
A Proposal of Equivalence Classes in Maximally Asymmetric Functions and Their Application to Benchmark Generation. ISMVL 2024: 59-64- 2023
- [j10]Gaku Kataoka, Masahiro Yamamoto, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi:
Feature Vectors Based on Wire Width and Distance for Lithography Hotspot Detection. IPSJ Trans. Syst. LSI Des. Methodol. 16: 2-11 (2023)
2010 – 2019
- 2018
- [c12]Yuri Itotani, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi:
An Approximate Nearest Neighbor Search Algorithm Using Distance-Based Hashing. DEXA (2) 2018: 203-213 - [c11]Gaku Kataoka, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi:
Novel Feature Vectors Considering Distances between Wires for Lithography Hotspot Detection. DSD 2018: 85-90 - [c10]Toshitaka Ito, Yuri Itotani, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi:
A Nearest Neighbor Search Engine Using Distance-Based Hashing. FPT 2018: 150-157 - 2016
- [c9]Yuto Arai, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi:
An efficient FPGA implementation of Mahalanobis distance-based outlier detection for streaming data. FPT 2016: 257-260 - 2015
- [j9]Masato Inagi, Yuichi Nakamura, Yasuhiro Takashima, Shin'ichi Wakabayashi:
Inter-FPGA Routing for Partially Time-Multiplexing Inter-FPGA Signals on Multi-FPGA Systems with Various Topologies. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(12): 2572-2583 (2015) - 2014
- [j8]Yoichi Wakaba, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi:
An Area Efficient Regular Expression Matching Engine Using Partial Reconfiguration for Quick Pattern Updating. Inf. Media Technol. 9(4): 466-474 (2014) - [j7]Yoichi Wakaba, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi:
An Area Efficient Regular Expression Matching Engine Using Partial Reconfiguration for Quick Pattern Updating. IPSJ Trans. Syst. LSI Des. Methodol. 7: 110-118 (2014) - [c8]Hiroki Nishiyama, Masato Inagi, Shin'ichi Wakabayashi, Shinobu Nagayama, Keisuke Inoue, Mineo Kaneko:
An ILP-Based Optimal Circuit Mapping Method for PLDs. IPDPS Workshops 2014: 251-256 - 2013
- [c7]Yoichi Wakaba, Shinobu Nagayama, Shin'ichi Wakabayashi, Masato Inagi:
A Flexible and Compact Regular Expression Matching Engine Using Partial Reconfiguration for FPGA. DSD 2013: 293-296 - [c6]Yasuhiro Shintani, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi:
A Multithreaded Parallel Global Routing Method with Overlapped Routing Regions. DSD 2013: 591-597 - 2012
- [j6]Masatoshi Nakamura, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka, Masayuki Sato, Takashi Ishiguro:
A Physical Design Method for a New Memory-Based Reconfigurable Architecture without Switch Blocks. IEICE Trans. Inf. Syst. 95-D(2): 324-334 (2012) - 2011
- [c5]Yoichi Wakaba, Masato Inagi, Shin'ichi Wakabayashi, Shinobu Nagayama:
An Efficient Hardware Matching Engine for Regular Expression with Nested Kleene Operators. FPL 2011: 157-161 - [c4]Masatoshi Nakamura, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka, Masayuki Sato, Takashi Ishiguro:
EDA Environment for Evaluating a New Switch-Block-Free Reconfigurable Architecture. ReConFig 2011: 448-454 - 2010
- [j5]Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura:
Globally Optimal Time-multiplexing of Inter-FPGA Connections for Multi-FPGA Prototyping Systems. Inf. Media Technol. 5(2): 388-397 (2010) - [j4]Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura:
Globally Optimal Time-multiplexing of Inter-FPGA Connections for Multi-FPGA Prototyping Systems. IPSJ Trans. Syst. LSI Des. Methodol. 3: 81-90 (2010)
2000 – 2009
- 2009
- [c3]Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura:
Globally optimal time-multiplexing in inter-FPGA connections for accelerating multi-FPGA systems. FPL 2009: 212-217 - 2008
- [j3]Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Atsushi Takahashi
:
Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3539-3547 (2008) - [c2]Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Atsushi Takahashi:
ILP-based optimization of time-multiplexed I/O assignment for multi-FPGA systems. ISCAS 2008: 1800-1803 - 2007
- [j2]Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Yoji Kajitani:
A Performance-Driven Circuit Bipartitioning Method Considering Time-Multiplexed I/Os. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(5): 924-931 (2007) - 2006
- [c1]Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Yoji Kajitani:
A performance-driven circuit bipartitioning algorithm for multi-FPGA implementation with time-multiplexed I/Os. FPT 2006: 361-364 - 2002
- [j1]Kengo R. Azegami, Masato Inagi, Atsushi Takahashi, Yoji Kajitani:
An Improvement of Network-Flow Based Multi-Way Circuit Partitioning Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(3): 655-663 (2002)
Coauthor Index
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