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ORCIDPing-Hsuan Hsieh
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2020 – today
- 2024
[c19]Yen-Po Lin
, Pen-Jui Peng, Chun-Chang Lu, Po-Ting Shen, Yun-Cheng Jao, Ping-Hsuan Hsieh:
7.7 A 2.16pJ/b 112Gb/s PAM-4 Transceiver with Time-Interleaved 2b/3b ADCs and Unbalanced Baud-Rate CDR for XSR Applications in 28nm CMOS. ISSCC 2024: 136-138- 2022
- [j13]Kunal Yadav, Ping-Hsuan Hsieh, Anthony Chan Carusone:
Loop Dynamics Analysis of PAM-4 Mueller-Muller Clock and Data Recovery System. IEEE Open J. Circuits Syst. 3: 216-227 (2022) - [j12]Ping-Hsuan Hsieh, Vanessa Chen:
Introduction to the Special Section on Smart Imaging. IEEE Open J. Circuits Syst. 3: 309-310 (2022) - 2021
- [j11]Friedel Gerfers, Ping-Hsuan Hsieh, Dejan Markovic, Jun Deguchi, Eric Karl:
Introduction to the Special Issue on the 2020 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits 56(1): 3-6 (2021) - [j10]Ping-Hsuan Hsieh, Chun-Ming Hsu, Yunzhi Dong:
Introduction to the Special Section on High-Speed Wireline and Optical Communication Circuits and Systems. IEEE Open J. Circuits Syst. 2: 32-33 (2021) - [c18]Yi-Cheng Lin, Ping-Hsuan Hsieh, Jian-Lun Hong, Yu-Hsiang Lai, Jun-Da Chen, Fan-Yi Lin, Yuan-Hao Huang, Po-Chiun Huang:
A Cross-Correlation-Based Time-of-Flight Design for Chaos Lidar Systems. A-SSCC 2021: 1-3 - [c17]Ping-Hsuan Hsieh, Mingoo Seok, Keith A. Bowman:
Session 29 Overview: Digital Circuits for Computing, Clocking and Power Management DIGITAL CIRCUITS SUBCOMMITTEE. ISSCC 2021: 402-403 - [c16]Nick Van Helleputte, Arijit Raychowdhury, Ping-Hsuan Hsieh, Jun Deguchi, Matteo Perenzoni, Esther Rodríguez-Villegas, Long Yan, Andreia Cathelin, Keith A. Bowman, Chris Van Hoof:
F3: Silicon Technologies in the Fight Against Pandemics - From Point of Care to Computational Epidemiology. ISSCC 2021: 520-524 - 2020
- [c15]Fu-Wen Chang, Ping-Hsuan Hsieh:
A 13.56-MHz Wireless Power Transfer Transmitter with Impedance Compression Network for Biomedical Applications. ISCAS 2020: 1-5 - [c14]Yu-Shyang Huang, Hung-Chen Chen, Ping-Hsuan Hsieh, Yi-Chung Shu:
A Calibration Technique for P-SSHI-Phi Interface for Piezoelectric Energy Harvesting. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [c13]Ping-Hsuan Hsieh, Ming-Li Tang, Sheng-Yen Hsu, Meng-Hung Lin, Yi-Hsiu Chen:
Design and Implementation of a Memristor-Based Oscillator. ISCAS 2019: 1-4 - [c12]Ming-Ting Wu, Hao-Che Hsu, Ping-Hsuan Hsieh:
A Digital-to-Time Converter with Coupled Phase-Rotating LC Oscillators in 90-nm CMOS Technology. ISCAS 2019: 1-4 - 2018
- [j9]Shih-Wei Wang, Yi-Wen Ke, Po-Chiun Huang, Ping-Hsuan Hsieh:
Electromagnetic Energy Harvester Interface Design for Wearable Applications. IEEE Trans. Circuits Syst. II Express Briefs 65-II(5): 667-671 (2018) - 2017
- [c11]Hsin-Tzu Lin, Yi-Chung Wu, Ping-Hsuan Hsieh, Chia-Hsiang Yang:
Integration of energy-recycling logic and wireless power transfer for ultra-low-power implantables. ISCAS 2017: 1-4 - 2016
- [j8]Cheng-Yen Lee, Ping-Hsuan Hsieh, Chia-Hsiang Yang:
A Standard-Cell-Design-Flow Compatible Energy-Recycling Logic With 70% Energy Saving. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(1): 70-79 (2016) - [c10]Chi-Huan Chen, Hung-Chen Chen, Yu-Shyang Huang, Ping-Hsuan Hsieh, Ping-Hsien Wu, Yi-Chung Shu:
A series-SSHI-Phi interface circuit for piezoelectric energy harvesting with 163% improvement in extracted power at off-resonance. A-SSCC 2016: 29-32 - [c9]Erik Jan Marinissen, Yervant Zorian, Mario Konijnenburg, Chih-Tsun Huang, Ping-Hsuan Hsieh, Peter Cockburn, Jeroen Delvaux, Vladimir Rozic, Bohan Yang, Dave Singelée, Ingrid Verbauwhede, Cedric Mayor, Robert Van Rijsinge, Cocoy Reyes:
IoT: Source of test challenges. ETS 2016: 1-10 - 2015
- [j7]Jen-Huan Tsai, Hui-Huan Wang, Yang-Chi Yen, Chang-Ming Lai, Yen-Ju Chen, Po-Chiun Huang, Ping-Hsuan Hsieh, Hsin Chen, Chao-Cheng Lee:
A 0.003 mm2 10 b 240 MS/s 0.7 mW SAR ADC in 28 nm CMOS With Digital Error Correction and Correlated-Reversed Switching. IEEE J. Solid State Circuits 50(6): 1382-1398 (2015) - [j6]Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F. Bulzacchelli, Mark A. Ferriss, Herschel A. Ainspan, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Christian W. Baks, Lei Shan, Young Hoon Kwark, José A. Tierno, Daniel J. Friedman:
A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology. IEEE J. Solid State Circuits 50(8): 1917-1931 (2015) - [j5]Ping-Hsuan Hsieh, Chih-Hsien Chou, Tao Chiang:
An RF Energy Harvester With 44.1% PCE at Input Available Power of -12 dBm. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(6): 1528-1537 (2015) - [c8]Chih-Hsien Chou, Ping-Hsuan Hsieh:
A 100-MHz radio-frequency energy harvester for passively powered devices. ECCTD 2015: 1-4 - 2014
- [c7]Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F. Bulzacchelli, Mark A. Ferriss, Herschel A. Ainspan, Alexander V. Rylyakov, Benjamin D. Parker, Christian W. Baks, Lei Shan, Young Hoon Kwark, José A. Tierno, Daniel J. Friedman:
A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology. CICC 2014: 1-4 - [c6]Yu-Hsien Kao, Chang-Ming Lai, Jen-Ming Wu, Po-Chiun Huang, Ping-Hsuan Hsieh, Ta-Shun Chu:
28.3 A frequency-defined vernier digital-to-time converter for impulse radar systems in 65nm CMOS. ISSCC 2014: 474-475 - 2013
- [c5]Yong Liu, Ping-Hsuan Hsieh, Seongwon Kim, Jae-sun Seo, Robert K. Montoye, Leland Chang, José A. Tierno, Daniel J. Friedman:
A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI. ISSCC 2013: 400-401 - 2012
- [j4]John F. Bulzacchelli, Christian Menolfi, Troy J. Beukema, Daniel W. Storaska, Juergen Hertle, David Hanson, Ping-Hsuan Hsieh, Sergey V. Rylov, Daniel Furrer, Daniele Gardellini, Andrea Prati, Thomas Morf, Vivek Sharma, Ram Kelkar, Herschel A. Ainspan, William R. Kelly, L. R. Chieco, Glenn Ritter, J. A. Sorice, Jon Garlett, Robert Callan, Matthias Braendli, Peter Buchmann, Marcel A. Kossel, Thomas Toifl, Daniel J. Friedman:
A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology. IEEE J. Solid State Circuits 47(12): 3232-3248 (2012) - [c4]John F. Bulzacchelli, Troy J. Beukema, Daniel W. Storaska, Ping-Hsuan Hsieh, Sergey V. Rylov, Daniel Furrer, Daniele Gardellini, Andrea Prati, Christian Menolfi, David Hanson, Juergen Hertle, Thomas Morf, Vivek Sharma, Ram Kelkar, Herschel A. Ainspan, William R. Kelly, Glenn Ritter, Jon Garlett, Robert Callan, Thomas Toifl, Daniel J. Friedman:
A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology. ISSCC 2012: 324-326 - 2010
- [j3]Ping-Hsuan Hsieh, Jay Maxey, Chih-Kong Ken Yang:
A Phase-Selecting Digital Phase-Locked Loop With Bandwidth Tracking in 65-nm CMOS Technology. IEEE J. Solid State Circuits 45(4): 781-792 (2010)
2000 – 2009
- 2009
- [j2]Ping-Hsuan Hsieh, Jay Maxey, Chih-Kong Ken Yang:
Minimizing the Supply Sensitivity of a CMOS Ring Oscillator Through Jointly Biasing the Supply and Control Voltages. IEEE J. Solid State Circuits 44(9): 2488-2495 (2009) - [c3]Ping-Hsuan Hsieh, Jay Maxey, Chih-Kong Ken Yang:
A nonlinear phase detector for digital phase locked loops. CICC 2009: 335-338 - 2008
- [c2]Ping-Hsuan Hsieh, Jay Maxey, Chih-Kong Ken Yang:
Minimizing the supply sensitivity of CMOS ring oscillator by jointly biasing the supply and control voltage. CICC 2008: 531-534 - 2007
- [j1]Ping-Hsuan Hsieh, Chih-Kong Ken Yang:
Technique to Reduce the Resolution Requirement of Digitally Controlled Oscillators for Digital PLLs. IEEE Trans. Circuits Syst. II Express Briefs 54-II(3): 237-241 (2007) - 2003
- [c1]Ping-Hsuan Hsieh, Jack Judy, Chih-Kong Ken Yang:
CMOS LC oscillator using variable mean frequency. CICC 2003: 147-150
Coauthor Index
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