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ORCIDJuan Fernando Eusse
Person information
- affiliation: Silexica GmbH, Cologne, Germany
- affiliation: RWTH Aachen University, Institute for Communication Technologies and Embedded Systems, Germany
- affiliation: University of Brasilia, Department of Electrical Engineering, DF, Brazil
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2020 – today
- 2020
[c14]Gereon Führ, Ahmed Hallawa, Rainer Leupers, Gerd Ascheid, Juan Fernando Eusse:
3D Optimisation of Software Application Mappings on Heterogeneous MPSoCs. ARCS 2020: 56-68
2010 – 2019
- 2019
- [b1]Juan Fernando Eusse Giraldo:
ASIP algorithmic/architectural co-exploration based on high level performance estimation. RWTH Aachen University, Germany, 2019 - [j5]Gereon Führ
, Seyit Halil Hamurcu, Diego Pala, Thomas Grass, Rainer Leupers, Gerd Ascheid, Juan Fernando Eusse:
Automatic Energy-Minimized HW/SW Partitioning for FPGA-Accelerated MPSoCs. IEEE Embed. Syst. Lett. 11(3): 93-96 (2019) - [j4]Gereon Führ, Ahmed Hallawa, Rainer Leupers, Gerd Ascheid, Juan Fernando Eusse:
Multi-objective optimisation of software application mappings on heterogeneous MPSoCs: TONPET versus R2-EMOA. Integr. 69: 50-61 (2019) - 2017
- [j3]Miguel Angel Aguilar, Juan Fernando Eusse, Projjol Ray, Rainer Leupers, Gerd Ascheid, Weihua Sheng, Prashant Sharma:
Towards Parallelism Extraction for Heterogeneous Multicore Android Devices. Int. J. Parallel Program. 45(6): 1592-1624 (2017) - [c13]Miguel Angel Aguilar, Rainer Leupers, Gerd Ascheid, Juan Fernando Eusse:
Extraction of recursion level parallelism for embedded multicore systems. SAMOS 2017: 154-162 - [p1]Rainer Leupers, Miguel Angel Aguilar, Juan Fernando Eusse, Jerónimo Castrillón, Weihua Sheng:
MAPS: A Software Development Environment for Embedded Multicore Applications. Handbook of Hardware/Software Codesign 2017: 917-949 - 2016
- [c12]Juan Fernando Eusse, Francisco Fernandez, Rainer Leupers, Gerd Ascheid:
Concurrent memory subsystem and application optimization for ASIP design. SAMOS 2016: 1-10 - 2015
- [j2]Juan Fernando Eusse Giraldo, Christopher Williams, Rainer Leupers:
CoEx: A Novel Profiling-Based Algorithm/Architecture Co-Exploration for ASIP Design. ACM Trans. Reconfigurable Technol. Syst. 8(3): 17:1-17:16 (2015) - [c11]Miguel Angel Aguilar, Juan Fernando Eusse, Rainer Leupers, Gerd Ascheid, Maximilian Odendahl:
Extraction of Kahn Process Networks from While Loops in Embedded Software. HPCC/CSS/ICESS 2015: 1078-1085 - [c10]Miguel Angel Aguilar, Juan Fernando Eusse, Projjol Ray, Rainer Leupers, Gerd Ascheid, Weihua Sheng, Prashant Sharma:
Parallelism extraction in embedded software for android devices. SAMOS 2015: 9-17 - [c9]Juan Fernando Eusse, Luis Gabriel Murillo, Christopher McGirr, Rainer Leupers, Gerd Ascheid:
Application-Specific Architecture Exploration Based on Processor-Agnostic Performance Estimation. SCOPES 2015: 84-87 - 2014
- [c8]Juan Fernando Eusse, Rainer Leupers, Gerd Ascheid, Patrick Sudowe, Bastian Leibe, Tamon Sadasue:
A flexible ASIP architecture for connected components labeling in embedded vision applications. DATE 2014: 1-6 - [c7]Juan Fernando Eusse Giraldo, Christopher Williams, Luis Gabriel Murillo, Rainer Leupers, Gerd Ascheid:
Pre-architectural performance estimation for ASIP design based on abstract processor models. ICSAMOS 2014: 133-140 - 2013
- [c6]Juan Fernando Eusse, Christopher Williams, Rainer Leupers:
CoEx: A novel profiling-based algorithm/architecture co-exploration for ASIP design. ReCoSoC 2013: 1-8 - 2012
- [j1]Juan Fernando Eusse Giraldo, Nahri Moreano, Alba Cristina Magalhaes Alves de Melo, Ricardo Pezzuol Jacobi:
A Protein Sequence Analysis Hardware Accelerator Based on Divergences. Int. J. Reconfigurable Comput. 2012: 201378:1-201378:19 (2012) - [c5]Luis Gabriel Murillo, Juan Fernando Eusse, Jovana Jovic, Sergey Yakoushkin, Rainer Leupers, Gerd Ascheid:
Synchronization for hybrid MPSoC full-system simulation. DAC 2012: 121-126 - [c4]Jovana Jovic, Sergey Yakoushkin, Luis Gabriel Murillo, Juan Fernando Eusse, Rainer Leupers, Gerd Ascheid:
Hybrid simulation for extensible processor cores. DATE 2012: 288-291 - 2010
- [c3]Juan Fernando Eusse Giraldo, Nahri Moreano, Ricardo Pezzuol Jacobi, Alba Cristina Magalhaes Alves de Melo:
A HMMER hardware accelerator using divergences. DATE 2010: 405-410
2000 – 2009
- 2009
- [c2]Juan Fernando Eusse Giraldo, Ricardo Pezzuol Jacobi:
Signal Processing Domain Application Mapping on the Brick Reconfigurable Array. ReConFig 2009: 356-361 - [c1]Juan Fernando Eusse Giraldo, Michael Hübner, Ricardo Pezzuol Jacobi:
BRICK: a multi-context expression grained reconfigurable architecture. SBCCI 2009
Coauthor Index
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