default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDT. M. Mak
This is just a disambiguation page, and is not intended to be the bibliography of an actual person. Any publication listed on this page has not been assigned to an actual author yet. If you know the true author of one of the publications listed below, you are welcome to contact us.
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
2020 – today
- 2020
[j17]Louis Y. Ungar, Neil G. Jacobson, T. M. Mak:
High-speed I/O capabilities added to military automatic test equipment (ATE) using synthetic instruments. IEEE Instrum. Meas. Mag. 23(5): 19-26 (2020)
2010 – 2019
- 2017
- [j16]Jae Woong Jeong, Vishwanath Natarajan, Shreyas Sen, T. M. Mak, Jennifer Kitchen, Sule Ozev:
A Comprehensive BIST Solution for Polar Transceivers Using On-Chip Resources. ACM Trans. Design Autom. Electr. Syst. 23(1): 2:1-2:21 (2017) - 2015
- [j15]Martin Omaña, Daniele Rossi
, Daniele Giaffreda, Cecilia Metra, T. M. Mak, Asifur Rahman, Simon Tam:
Low-Cost On-Chip Clock Jitter Measurement Scheme. IEEE Trans. Very Large Scale Integr. Syst. 23(3): 435-443 (2015) - 2014
- [j14]Daniele Rossi, Martin Omaña, José Manuel Cazeaux, Cecilia Metra, T. M. Mak:
Clock Faults Induced Min and Max Delay Violations. J. Electron. Test. 30(1): 111-123 (2014) - [c47]T. M. Mak:
Interposer test: Testing PCBs that have shrunk 100x. ITC 2014: 1 - [c46]John Kim, Wolfgang Meyer, T. M. Mak, Amitava Majumdar:
Innovative practices session 3C: Solving today's test challenges. VTS 2014: 1 - 2013
- [c45]Jae Woong Jeong, Sule Ozev, Shreyas Sen, T. M. Mak:
Measurement of envelope/phase path delay skew and envelope path bandwidth in polar transmitters. VTS 2013: 1-6 - 2012
- [j13]Cecilia Metra, Martin Omaña, T. M. Mak, Simon Tam:
New Design for Testability Approach for Clock Fault Testing. IEEE Trans. Computers 61(4): 448-457 (2012) - [j12]Li Jiang, Qiang Xu, Krishnendu Chakrabarty, T. M. Mak:
Integrated Test-Architecture Optimization and Thermal-Aware Test Scheduling for 3-D SoCs Under Pre-Bond Test-Pin-Count Constraint. IEEE Trans. Very Large Scale Integr. Syst. 20(9): 1621-1633 (2012) - 2011
- [j11]Martin Omaña, Cecilia Metra, T. M. Mak, Simon Tam:
Low-Cost Dynamic Compensation Scheme for Local Clocks of Next Generation High Performance Microprocessors. IEEE Trans. Very Large Scale Integr. Syst. 19(12): 2322-2325 (2011) - 2010
- [c44]Martin Omaña, Daniele Giaffreda, Cecilia Metra, T. M. Mak, Simon Tam, Asifur Rahman:
On-die Ring Oscillator Based Measurement Scheme for Process Parameter Variations and Clock Jitter. DFT 2010: 265-272
2000 – 2009
- 2009
- [c43]Li Jiang, Qiang Xu, Krishnendu Chakrabarty, T. M. Mak:
Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint. ICCAD 2009: 191-196 - [c42]Joon-Sung Yang, Nur A. Touba, Shih-Yu Yang, T. M. Mak:
An industrial case study for X-canceling MISR. ITC 2009: 1-10 - 2008
- [c41]Cecilia Metra, Martin Omaña, T. M. Mak, Asifur Rahman, Simon Tam:
Novel On-Chip Clock Jitter Measurement Scheme for High Performance Microprocessors. DFT 2008: 465-473 - [c40]T. M. Mak:
Jitters in high performance microprocessors. ITC 2008: 1-6 - 2007
- [j10]T. M. Mak:
The case for power with test. IEEE Des. Test Comput. 24(3): 296 (2007) - [j9]Cecilia Metra, Daniele Rossi, T. M. Mak:
Won't On-Chip Clock Calibration Guarantee Performance Boost and Product Quality?. IEEE Trans. Computers 56(3): 415-428 (2007) - [c39]T. M. Mak:
Invited Talk 1: Testing of Power Constraint Computing. ATS 2007: 6 - [c38]Ming Zhang, T. M. Mak, James W. Tschanz, Kee Sup Kim, Norbert Seifert, Davia Lu:
Design for Resilience to Soft Errors and Variations. IOLTS 2007: 23-28 - [c37]T. M. Mak:
Infant Mortality--The Lesser Known Reliability Issue. IOLTS 2007: 122 - [c36]Rajesh Thirugnanam, Dong Sam Ha, T. M. Mak:
Data Recovery Block Design for Impulse Modulated Power Line Communications in a Microprocessor. ISVLSI 2007: 153-158 - [c35]Cecilia Metra, Martin Omaña, T. M. Mak, Simon Tam:
Novel compensation scheme for local clocks of high performance microprocessors. ITC 2007: 1-9 - [c34]Cecilia Metra, Martin Omaña, T. M. Mak, Simon Tam:
Novel Approach to Clock Fault Testing for High Performance Microprocessors. VTS 2007: 441-446 - 2006
- [j8]Kaushik Roy, T. M. Mak, Kwang-Ting (Tim) Cheng:
Test Consideration for Nanometer-Scale CMOS Circuits. IEEE Des. Test Comput. 23(2): 128-136 (2006) - [j7]T. M. Mak:
Is System in Package the Panacea for Integration? IEEE Des. Test Comput. 23(3): 256 (2006) - [j6]T. M. Mak, Sani R. Nassif:
Guest Editors' Introduction: Process Variation and Stochastic Design and Test. IEEE Des. Test Comput. 23(6): 436-437 (2006) - [j5]Ming Zhang, Subhasish Mitra, T. M. Mak, Norbert Seifert, Nicholas J. Wang, Quan Shi, Kee Sup Kim, Naresh R. Shanbhag, Sanjay J. Patel:
Sequential Element Design With Built-In Soft Error Resilience. IEEE Trans. Very Large Scale Integr. Syst. 14(12): 1368-1378 (2006) - [c33]Cecilia Metra, Daniele Rossi, Martin Omaña, José Manuel Cazeaux, T. M. Mak:
Can Clock Faults be Detected Through Functional Test? DDECS 2006: 168-173 - [c32]Arani Sinha, Shahin Nazarian, T. M. Mak:
Simulating the Effects of Process Variations on Capacitive Crosstalk. ICECS 2006: 604-607 - [c31]Cecilia Metra, Martin Omaña, Daniele Rossi, José Manuel Cazeaux, T. M. Mak:
Path (Min) Delay Faults and Their Impact on Self-Checking Circuits' Operation. IOLTS 2006: 17-22 - [c30]T. M. Mak:
Test Challenges for 3D Circuits. IOLTS 2006: 79 - [c29]T. M. Mak, Subhasish Mitra:
Should Logic SER be Solved at the Circuit Level? IOLTS 2006: 199 - [c28]Subhasish Mitra, Ming Zhang, Norbert Seifert, T. M. Mak, Kee Sup Kim:
Soft Error Resilient System Design through Error Correction. VLSI-SoC (Selected Papers) 2006: 143-156 - [c27]Subhasish Mitra, Ming Zhang, Norbert Seifert, T. M. Mak, Kee Sup Kim:
Soft Error Resilient System Design through Error Correction. VLSI-SoC 2006: 332-337 - [c26]Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De, T. M. Mak:
Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware Design. VLSI Design 2006: 606-612 - 2005
- [c25]T. M. Mak:
Limitation of structural scan delay test. Asian Test Symposium 2005: 471 - [c24]Cecilia Metra, Martin Omaña, Daniele Rossi, José Manuel Cazeaux, T. M. Mak:
The Other Side of the Timing Equation: a Result of Clock Faults. DFT 2005: 169-177 - [c23]T. M. Mak, Subhasish Mitra, Ming Zhang:
DFT Assisted Built-In Soft Error Resilience. IOLTS 2005: 69 - [c22]T. M. Mak:
Does It Mean Less Testing for Self Calibrating Design?. IOLTS 2005: 99 - [c21]Subhasish Mitra, Ming Zhang, T. M. Mak, Norbert Seifert, Victor Zia, Kee Sup Kim:
Logic soft errors: a major barrier to robust platform design. ITC 2005: 10 - [c20]Leonard Lee, Li-C. Wang, Praveen Parvathala, T. M. Mak:
On Silicon-Based Speed Path Identification. VTS 2005: 35-41 - 2004
- [j4]Melvin A. Breuer, Sandeep K. Gupta, T. M. Mak:
Defect and Error Tolerance in the Presence of Massive Numbers of Defects. IEEE Des. Test Comput. 21(3): 216-227 (2004) - [j3]T. M. Mak, Angela Krstic, Kwang-Ting (Tim) Cheng, Li-C. Wang:
New Challenges in Delay Testing of Nanometer, Multigigahertz Designs. IEEE Des. Test Comput. 21(3): 241-247 (2004) - [j2]T. M. Mak, Mike Tripp, Anne Meixner:
Testing Gbps Interfaces without a Gigahertz Tester. IEEE Des. Test Comput. 21(4): 278-286 (2004) - [j1]Cecilia Metra, Stefano Di Francescantonio, T. M. Mak:
Implications of Clock Distribution Faults and Issues with Screening Them during Manufacturing Testing. IEEE Trans. Computers 53(5): 531-546 (2004) - [c19]Cecilia Metra, T. M. Mak, Martin Omaña:
Fault secureness need for next generation high performance microprocessor design for testability structures. Conf. Computing Frontiers 2004: 444-450 - [c18]Mike Tripp, T. M. Mak, Anne Meixner:
Design considerations and DFT to enable testing of digital interfaces. CICC 2004: 197-205 - [c17]Li-C. Wang, T. M. Mak, Kwang-Ting Cheng, Magdy S. Abadir:
On path-based learning and its applications in delay test and diagnosis. DAC 2004: 492-497 - [c16]Cecilia Metra, T. M. Mak, Martin Omaña:
Are Our Design for Testability Features Fault Secure? DATE 2004: 714-715 - [c15]Leonard Lee, Li-C. Wang, T. M. Mak, Kwang-Ting Cheng:
A path-based methodology for post-silicon timing validation. ICCAD 2004: 713-720 - [c14]Eric F. Weglarz, Kewal K. Saluja, T. M. Mak:
Testing of Hard Faults in Simultaneous Multithreaded Processors. IOLTS 2004: 95-100 - [c13]Sandip Kundu, T. M. Mak, Rajesh Galivanche:
Trends in manufacturing test methods and their implications. ITC 2004: 679-687 - [c12]Cecilia Metra, T. M. Mak, Martin Omaña:
Risks Associated with Faults within Test Pattern Compactors and Their Implications on Testing. ITC 2004: 1223-1231 - [c11]Mike Tripp, T. M. Mak, Anne Meixner:
Elimination of Traditional Functional Testing of Interface Timings at Intel. ITC 2004: 1448-1456 - [c10]Michael Spica, T. M. Mak:
Do We Need Anything More Than Single Bit Error Correction (ECC)? MTDT 2004: 111-116 - 2003
- [c9]Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, T. M. Mak:
Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models. DAC 2003: 668-673 - [c8]Cecilia Metra, T. M. Mak, Daniele Rossi:
Clock Calibration Faults and their Impact on Quality of High Performance Microprocessors. DFT 2003: 63-70 - [c7]Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, T. M. Mak:
Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and Methodologies. ITC 2003: 339-348 - [c6]Mike Tripp, T. M. Mak, Anne Meixner:
Elimination of Traditional Functional Testing of Interface Timings at Intel. ITC 2003: 1014-1022 - [c5]Kaushik Roy, T. M. Mak, Kwang-Ting Cheng:
Embedded Tutorial: Test Consideration for Nanometer Scale CMOS Circuits. VTS 2003: 313-318 - 2002
- [c4]Cecilia Metra, Stefano Di Francescantonio, T. M. Mak:
Clock Faults? Impact on Manufacturing Testing and Their Possible Detection Through On-Line Testing. ITC 2002: 100-109 - 2001
- [c3]Cecilia Metra, Stefano Di Francescantonio, Bruno Riccò, T. M. Mak:
Evaluation of Clock Distribution Networks' Most Likely Faults and Produced Effects. DFT 2001: 357-365 - [c2]Liang-Chi Chen, T. M. Mak, Sandeep K. Gupta, Melvin A. Breuer:
Crosstalk test generation on pseudo industrial circuits: a case study. ITC 2001: 548-557
1990 – 1999
- 1998
- [c1]T. M. Mak, Debika Bhattacharya, Cheryl Prunty, Bob Roeder, Nermine Ramadan, F. Joel Ferguson, Jianlin Yu:
Cache RAM inductive fault analysis with fab defect modeling. ITC 1998: 862-871
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-04-25 05:47 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
