"Loop-based interconnect modeling and optimization approach for multi-GHz ..."

Xuejue Huang et al. (2002)

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DOI: 10.1109/CICC.2002.1012758

access: closed

type: Conference or Workshop Paper

metadata version: 2024-08-01

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Xuejue Huang, Phillip J. Restle, Thomas J. Bucelot, Yu Cao, Tsu-Jae King:
Loop-based interconnect modeling and optimization approach for multi-GHz clock network design. CICC 2002: 19-22

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