"A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP ..."

Shayan Shahramian, Anthony Chan Carusone (2015)

> Home

Details and statistics

DOI: 10.1109/JSSC.2015.2402218

access: closed

type: Journal Article

metadata version: 2020-08-30

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jssc/ShahramianC15
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/ShahramianC15
Shayan Shahramian, Anthony Chan Carusone:
A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS. IEEE J. Solid State Circuits 50(7): 1722-1735 (2015)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.