"ASIC design of power and area efficient programmable FIR filter using ..."

Sudhanshu Janwadkar, Rasika Dhavse (2024)

> Home

Details and statistics

DOI: 10.1016/J.MICPRO.2024.105048

access: closed

type: Journal Article

metadata version: 2024-08-04

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/mam/JanwadkarD24
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/mam/JanwadkarD24
Sudhanshu Janwadkar, Rasika Dhavse:
ASIC design of power and area efficient programmable FIR filter using optimized Urdhva-Tiryagbhyam Multiplier for impedance cardiography. Microprocess. Microsystems 107: 105048 (2024)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.