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ORCIDMicroprocessors and Microsystems, Volume 65
Volume 65, March 2019
- Yasir Naseer, Dawood Shah, Tariq Shah:
A novel approach to improve multimedia security utilizing 3D mixed chaotic map. 1-6 - Kim Bjerge
, Hans O. U. Fynbo, Jacob G. Johansen:
A system on programmable chip design of a digitizer with improved trapezoidal filter validation. 7-13 - Mingyu Wang, Zhaolin Li:
An area- and energy-efficient hybrid architecture for floating-point FFT computations. 14-22 - Johan Fjeldtvedt, Milica Orlandic:
CubeDMA - Optimizing three-dimensional DMA transfers for hyperspectral imaging applications. 23-36 - Miroslaw Chmiel:
FPGA-based implementation of bistable function blocks defined in the IEC 61131. 37-46 - Geethu Sathees Babu, Gopalakrishnan Lakshminarayanan:
Reconfigurable address generator for multi-standard interleaver. 47-56 - Shereen Afifi, Hamid Gholamhosseini, Roopak Sinha:
A system on chip for melanoma detection using FPGA-based SVM classifier. 57-68 - Jihe Wang, Danghui Wang:
A smart protocol-level task mapping for energy efficient traffic on network-on-chip. 69-78 - S. Navid Shahrouzi, Darshika G. Perera:
Optimized hardware accelerators for data mining applications on embedded platforms: Case study principal component analysis. 79-96 - Kaliannan Sivanandam, P. Kumar:
Design and performance analysis of reconfigurable modified Vedic multiplier with 3-1-1-2 compressor. 97-106 - Joseph Anthony Prathap, T. S. Anandhi:
A novel parallel duty cycle control algorithm for photovoltaic voltage regulator system using FPGA. 107-120 - Francisco Nombela, Enrique García, Raúl Mateos, Álvaro Hernández:
Real-time architecture for channel estimation and equalization in broadband PLC. 121-135 - Libo Huang, Ya-Shuai Lü, Sheng Ma, Nong Xiao, Zhiying Wang:
SIMD stealing: Architectural support for efficient data parallel execution on multicores. 136-147 - Adnan Rauf, Muhammad Adeel Pasha, Shahid Masud:
Towards design and automation of a scalable split-radix FFT processor for high throughput applications. 148-157 - Moumita Chakraborty, Debasri Saha, Amlan Chakrabarti, Sayani Bindai:
A CAD approach for pre-layout optimal PDN design and its post-layout verification. 158-168
- Siyuan Xu, Shuangnan Liu, Yidi Liu, Anushree Mahapatra, Monica Villaverde, Félix Moreno, Benjamin Carrión Schäfer:
Design space exploration of heterogeneous MPSoCs with variable number of hardware accelerators. 169-179 - Anirban Chakraborty, Ayan Banerjee:
Modular and parallel VLSI architecture of multi-dimensional quad-core GA co-processor for real time image/video processing. 180-195
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