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ORCIDVLSI Design, Volume 4
Volume 4, Number 1, 1996
- Dinesh Bhatia
, Amit Chowdhary:
A Multi-Terminal Net Router for Field-Programmable Gate Arrays. 1-10 - Jin-Tai Yan, Pei-Yung Hsiao:
An O(NlogN) Algorithm for Region Definition Using Channels/Switchboxes and Ordering Assignment. 11-16 - Pei-Yung Hsiao:
Nearly Balanced Quad List Quad Tree -A Data Structure for VLSI Layout Systems. 17-32 - Dharmavani Bhagavathi, Himabindu Gurla, Stephan Olariu, James L. Schwing, Jingyuan Zhang:
Time- and Cost-Optimal Parallel Algorithms for the Dominance and Visibility Graphs. 33-40 - Jai-Shen Huang, Yeh-Hao Chin:
An Efficient Algorithm for the Split K-Layer Circular Topological Via Minimization Problem. 41-51 - Sunil Chopra, Kalyan T. Talluri:
Minimum-Cost Node-Disjoint Steiner Trees in Series-Parallel Networks. 53-57 - Ausif Mahmood:
Behavioral Simulation and Performance Evaluation of Multi-Processor Architectures. 59-68 - A. Srivastava, S. R. Palavali:
Integration of SPICE with TEK LV500 ASIC Design Verification System. 69-74 - A. Srivastava, K. Venkatapathy:
Design and Implementation of a Low Power Ternary Full Adder. 75-81 - B. Majumdar, V. V. Ramakrishna, P. S. Dey, A. K. Majumdar:
Design of an ASIC Chip for Skeletonization of Graylevel Digital Images. 83-90
Volume 4, Number 2, 1996
- Ausif Mahmood:
Hardware Accelerators for VLSI Design. i-ii - Ausif Mahmood, William I. Baker:
An Evaluation of Parallel Synchronous and Conservative Asynchronous Logic-Level Simulations. 91-105 - E. Scott Fehr, Stephen A. Szygenda, Granville E. Ott:
An Integrated Hardware Array for Very High Speed Logic Simulation. 107-118 - Sungho Kang, Youngmin Hur, Stephen A. Szygenda:
A Hardware Accelerator for Fault Simulation Utilizing a Reconfigurable Array Architecture. 119-133 - Neil J. Howard, Andrew M. Tyrrell, Nigel M. Allinson:
The Use of Field-Programmable Gate Arrays for the Hardware Acceleration of Design Automation Tasks. 135-139 - Seokjin Kim, Ramalingam Sridhar:
Hardware Design Rule Checker Using a CAM Architecture. 141-147
Volume 4, Number 3, 1996
- Sunil R. Das:
Guest Editorial. i-iv - Wen-Ben Jone, Nigam Shah, Anita Gleason, Sunil R. Das:
PGEN: A Novel Approach to Sequential Circuit Test Generation. 149-165 - Ananta K. Majhi, James Jacob, Lalit M. Patnaik:
A Novel Path Delay Fault Simulator Using Binary Logic. 167-179 - Kyuchull Kim, Kewal K. Saluja:
HYSIM: Hybrid Fault Simulation for Synchronous Sequential Circuits. 181-197 - Geetani Edirisooriya:
Closed Form Aliasing Probability For Q-ary Symmetric Errors. 199-205 - M. Srinivas, L. M. Patnaik:
On Generating Optimal Signal Probabilities for Random Tests: A Genetic Approach. 207-215 - Evstratios Vandris, Gerald E. Sobelman:
Switch-level Differential Fault Simulation of MOS VLSI Circuits. 217-229 - Sankaran M. Menon, Yashwant K. Malaiya, Anura P. Jayasumana:
Fault Modeling of ECL for High Fault Coverage of Physical Defects. 231-242 - Anupam Basu, Dilip K. Banerji, Amit Basu, Thomas Charles Wilson, Jayanti C. Majithia:
A Modified Approach to Test Plan Generation for Combinational Logic Blocks. 243-256 - Subir Bandyopadhyay, Abhijit Sengupta, Bhargab B. Bhattacharya:
A Methodology for Testing Arbitrary Bilateral Bit-Level Systolic Arrays. 257-269 - Erratum. 271-274
Volume 4, Number 4, 1996
- Dinesh Bhatia:
Field-Programmable Gate Arrays. i-ii - Stephen Dean Brown, Muhammad M. Khellah, Guy Lemieux:
Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays. 275-291 - Kalapi Roy-Neogi, Bingzhong Guan, Carl Sechen:
A Sea-of-Gates Style FPGA Placement Algorithm. 293-307 - Kalapi Roy-Neogi, Carl Sechen:
A Timing-Driven Partitioning System for Multiple FPGAs. 309-328 - Don Cherepacha, David M. Lewis:
DP-FPGA: An FPGA Architecture Optimized for Datapaths. 329-343 - Srilata Raman, C. L. Liu, Larry G. Jones:
Timing-Constrained FPGA Placement: A Force-Directed Formulation and Its Performance Evaluation. 345-355
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