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2000 – 2009
- 2007
[j4]Jen-Chieh Yeh, Kuo-Liang Cheng, Yung-Fa Chou, Cheng-Wen Wu
:
Flash Memory Testing and Built-In Self-Diagnosis With March-Like Test Algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(6): 1101-1113 (2007)- [j3]Chih-Yen Lo, Chen-Hsing Wang, Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Shin-Moe Wang, Cheng-Wen Wu:
STEAC: A Platform for Automatic SOC Test Integration. IEEE Trans. Very Large Scale Integr. Syst. 15(5): 541-545 (2007) - 2005
- [c15]Chih-Pin Su, Chen-Hsing Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu:
Design and test of a scalable security processor. ASP-DAC 2005: 372-375 - 2004
- [c14]Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Chih-Yen Lo, Li-Ming Denq, Chih-Tsun Huang, Shin-Wei Hung, Jye-Yuan Lee:
An SOC Test Integration Platform and Its Industrial Realization. ITC 2004: 1213-1222 - 2003
- [c13]Kuo-Liang Cheng, Chih-Wea Wang, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu:
FAME: A Fault-Pattern Based Memory Failure Analysis Framework. ICCAD 2003: 595-598 - [c12]Chih-Wea Wang, Kuo-Liang Cheng, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu, Frank Huang, Hong-Tzer Yang:
Fault Pattern Oriented Defect Diagnosis for Memories. ITC 2003: 29-38 - [c11]Chih-Wea Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu:
Test and Diagnosis of Word-Oriented Multiport Memories. VTS 2003: 248-253 - 2002
- [j2]Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu:
Fault simulation and test algorithm generation for random accessmemories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(4): 480-490 (2002) - [j1]Kuo-Liang Cheng, Ming-Fu Tsai, Cheng-Wen Wu:
Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(11): 1328-1336 (2002) - [c10]Chih-Wea Wang, Jing-Reng Huang, Yen-Fu Lin, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin:
Test Scheduling of BISTed Memory Cores for SOC. Asian Test Symposium 2002: 356- - [c9]Huan-Shan Hsu, Jing-Reng Huang, Kuo-Liang Cheng, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin:
Test Scheduling and Test Access Architecture Optimization for System-on-Chip. Asian Test Symposium 2002: 411- - [c8]Jen-Chieh Yeh, Chi-Feng Wu, Kuo-Liang Cheng, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu:
Flash Memory Built-In Self-Test Using March-Like Algorithm. DELTA 2002: 137-141 - [c7]Kuo-Liang Cheng, Jen-Chieh Yeh, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu:
RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics. VTS 2002: 281-288 - 2001
- [c6]Kuo-Liang Cheng, Chia-Ming Hsueh, Jing-Reng Huang, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu:
Automatic Generation of Memory Built-in Self-Test Cores for System-on-Chip. Asian Test Symposium 2001: 91-96 - [c5]Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Chih-Wea Wang, Cheng-Wen Wu:
Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories. DAC 2001: 301-306 - [c4]Jin-Fu Li, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu:
March-based RAM diagnosis algorithms for stuck-at and coupling faults. ITC 2001: 758-767 - [c3]Kuo-Liang Cheng, Ming-Fu Tsai, Cheng-Wen Wu:
Efficient Neighborhood Pattern-Sensitive Fault Test Algorithms for Semiconductor Memories. VTS 2001: 225-230 - 2000
- [c2]Chi-Feng Wu, Chih-Tsun Huang, Chih-Wea Wang, Kuo-Liang Cheng, Cheng-Wen Wu:
Error Catch and Analysis for Semiconductor Memories Using March Tests. ICCAD 2000: 468-471 - [c1]Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu:
Simulation-Based Test Algorithm Generation for Random Access Memories. VTS 2000: 291-296
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