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ORCIDPrakash Narayanan
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2020 – today
- 2021
[c6]Krishnanshu Dandu, Sreekiran Samala, Karan Bhatia, Meysam Moallem, Karthik Subburaj, Zeshan Ahmad, Daniel Breen, Sunhwan Jang, Tim Davis, Mayank Singh, Shankar Ram, Vashishth Dudhia, Marc DeWilde, Dheeraj Shetty, John Samuel, Zahir Parkar, Cathy Chi, Pilar Loya, Zachary Crawford, John Herrington, Ross Kulak, Abhinav Daga, Rakesh Raavi, Ravi Teja, Rajesh Veettil, Daniel Khemraj, Indu Prathapan, Prakash Narayanan, Naveen Narayanan, Sangamesh Anandwade, Jasbir Singh, Venkatesh Srinivasan, Neeraj Nayak, Karthik Ramasubramanian, Brian P. Ginsburg
, Vijay Rentala:
High-Performance and Small Form-Factor mm-Wave CMOS Radars for Automotive and Industrial Sensing in 76-to-81GHz and 57-to-64GHz Bands. ISSCC 2021: 39-41
2010 – 2019
- 2017
- [c5]Wilson Pradeep, Prakash Narayanan, Rubin A. Parekhji:
An optimised SDD ATPG and SDQL computation method across different pattern sets. VTS 2017: 1-6 - 2014
- [c4]Prakash Narayanan, Satish Ravichandran, Balaji Ramayanam:
Novel self-test methods to reduce on-chip memory requirements and improved test coverage. IOLTS 2014: 198-199 - 2011
- [c3]Lakshmanan Balasubramanian, Puneet Sabbarwal, Rajesh Kumar Mittal, Prakash Narayanan, Ranjit Kumar Dash, Anand Devendra Kudari, Srikanth Manian, Sudhir Polarouthu, Harikrishna Parthasarathy, Ravi C. Vijayaraghavan, Sachin Turkewadikar:
Circuit and DFT techniques for robust and low cost qualification of a mixed-signal SoC with integrated power management system. DATE 2011: 551-554 - [c2]Rajesh Mittal, Lakshmanan Balasubramanian, Adesh Sontakke, Harikrishna Parthasarathy, Prakash Narayanan, Puneet Sabbarwal, Rubin A. Parekhji:
DFT for extremely low cost test of mixed signal SOCs with integrated RF and power management. ITC 2011: 1-10 - [c1]Prakash Narayanan, Rajesh Mittal, Sumanth Poddutur, Vivek Singhal, Puneet Sabbarwal:
Modified flip-flop architecture to reduce hold buffers and peak power during scan shift operation. VTS 2011: 154-159
Coauthor Index
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