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2020 – today
- 2024
[c8]Koichi Nose, Taro Fujii, Katsumi Togawa, Shunsuke Okumura, Kentaro Mikami, Daichi Hayashi, Teruhito Tanaka, Takao Toi:
20.3 A 23.9TOPS/W @ 0.8V, 130TOPS AI Accelerator with 16× Performance-Accelerable Pruning in 14nm Heterogeneous Embedded MPU for Real-Time Robot Applications. ISSCC 2024: 364-366- 2021
- [c7]Fukashi Morishita
, Norihito Kato, Satoshi Okubo, Takao Toi, Mitsuru Hiraki, Sugako Otani, Hideaki Abe, Yuji Shinohara, Hiroyuki Kondo:
A CMOS Image Sensor and an AI Accelerator for Realizing Edge-Computing-Based Surveillance Camera Systems. VLSI Circuits 2021: 1-2
2010 – 2019
- 2018
- [c6]Taro Fujii, Takao Toi, Teruhito Tanaka, Katsumi Togawa, Toshiro Kitaoka, Kengo Nishino, Noritsugu Nakamura, Hiroki Nakahara, Masato Motomura:
New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications. VLSI Circuits 2018: 41-42 - 2013
- [c5]Takao Toi, Noritsugu Nakamura, Taro Fujii, Toshiro Kitaoka, Katsumi Togawa, Koichiro Furuta, Toru Awashima:
Optimizing time and space multiplexed computation in a dynamically reconfigurable processor. FPT 2013: 106-111 - 2011
- [j5]Takao Toi, Takumi Okamoto, Toru Awashima, Kazutoshi Wakabayashi, Hideharu Amano:
Iterative Synthesis Methods Estimating Programmable-Wire Congestion in a Dynamically Reconfigurable Processor. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2619-2627 (2011) - 2010
- [j4]Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, Toru Awashima, Kazutoshi Wakabayashi:
High-level Synthesis Challenges for Mapping a Complete Program on a Dynamically Reconfigurable Processor. Inf. Media Technol. 5(2): 398-411 (2010) - [j3]Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, Toru Awashima, Kazutoshi Wakabayashi:
High-level Synthesis Challenges for Mapping a Complete Program on a Dynamically Reconfigurable Processor. IPSJ Trans. Syst. LSI Des. Methodol. 3: 91-104 (2010) - [c4]Takao Toi, Takumi Okamoto, Toru Awashima, Kazutoshi Wakabayashi, Hideharu Amano:
Wire congestion aware synthesis for a dynamically reconfigurable processor. FPT 2010: 300-303
2000 – 2009
- 2006
- [c3]Shohei Abe, Yohei Hasegawa, Takao Toi, Takeshi Inuo, Hideharu Amano:
An adaptive Viterbi decoder on the dynamically reconfigurable processor. FPT 2006: 285-288 - [c2]Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, Toru Awashima, Kazutoshi Wakabayashi, Li Jing:
High-level synthesis challenges and solutions for a dynamically reconfigurable processor. ICCAD 2006: 702-708 - 2004
- [c1]Masayasu Suzuki, Yohei Hasegawa, Yutaka Yamada, Naoto Kaneko, Katsuaki Deguchi, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takao Toi, Toru Awashima:
Stream applications on the dynamically reconfigurable processor. FPT 2004: 137-144 - 2000
- [j2]Takao Toi:
Color signal processing technique for single-chip CCD cameras that employ CPUs with SIMD instruction sets. IEEE Trans. Consumer Electron. 46(2): 291-294 (2000)
1990 – 1999
- 1999
- [j1]Takao Toi, M. Ohita:
A subband coding technique for image compression in single CCD cameras with Bayer color filter arrays. IEEE Trans. Consumer Electron. 45(1): 176-180 (1999)
Coauthor Index
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