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ORCIDInhak Han
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2010 – 2019
- 2019
[c8]Yonghwi Kwon, Inhak Han, Youngsoo Shin:
Clock Gating Synthesis of Netlist with Cyclic Logic Paths. ICCAD 2019: 1-6- 2018
- [j3]Inhak Han, Youngsoo Shin:
Folded Circuit Synthesis: Min-Area Logic Synthesis Using Dual-Edge-Triggered Flip-Flops. ACM Trans. Design Autom. Electr. Syst. 23(5): 61:1-61:21 (2018) - [c7]Yonghwi Kwon
, Jinwook Jung, Inhak Han, Youngsoo Shin:
Transient Clock Power Estimation of Pre-CTS Netlist. ISCAS 2018: 1-4 - 2016
- [c6]Inhak Han, Daijoon Hyun, Youngsoo Shin:
Buffer insertion to remove hold violations at multiple process corners. ASP-DAC 2016: 232-237 - [c5]Inhak Han, Jonggyu Kim, Joonhwan Yi, Youngsoo Shin:
Register grouping for synthesis of clock gating logic. ICICDT 2016: 1-4 - 2014
- [j2]Inhak Han, Youngsoo Shin:
Simplifying Clock Gating Logic by Matching Factored Forms. IEEE Trans. Very Large Scale Integr. Syst. 22(6): 1338-1349 (2014) - 2013
- [c4]Inhak Han, Youngsoo Shin:
Folded circuit synthesis: Logic simplification using dual edge-triggered flip-flops. ICICDT 2013: 17-20 - 2012
- [j1]Seungwhun Paik, Inhak Han, Sangmin Kim, Youngsoo Shin:
Clock Gating Synthesis of Pulsed-Latch Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(7): 1019-1030 (2012) - [c3]Inhak Han, Youngsoo Shin:
Synthesis of clock gating logic through factored form matching. ICICDT 2012: 1-4 - 2011
- [c2]Sangmin Kim, Inhak Han, Seungwhun Paik, Youngsoo Shin:
Pulser gating: A clock gating of pulsed-latch circuits. ASP-DAC 2011: 190-195 - [c1]Jaeha Kung, Inhak Han, Sachin S. Sapatnekar, Youngsoo Shin:
Thermal signature: a simple yet accurate thermal index for floorplan optimization. DAC 2011: 108-113
Coauthor Index
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