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2010 – 2019
- 2016
[c3]Li-Chung Hsu, Junichiro Kadomoto, So Hasegawa, Atsutake Kosuge, Yasuhiro Take, Tadahiro Kuroda:
Analytical thruchip inductive coupling channel design optimization. ASP-DAC 2016: 731-736- 2015
- [j3]Li-Chung Hsu, Masato Motomura
, Yasuhiro Take, Tadahiro Kuroda:
Through Chip Interface Based Three-Dimensional FPGA Architecture Exploration. IEICE Trans. Electron. 98-C(4): 288-297 (2015) - [j2]Li-Chung Hsu, Junichiro Kadomoto, So Hasegawa, Atsutake Kosuge, Yasuhiro Take, Tadahiro Kuroda:
A Study of Physical Design Guidelines in ThruChip Inductive Coupling Channel. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(12): 2584-2591 (2015) - [c2]Li-Chung Hsu, Yasuhiro Take, Atsutake Kosuge, So Hasegawa, Junichiro Kadamoto, Tadahiro Kuroda:
Design and analysis for ThruChip design for manufacturing (DFM). ASP-DAC 2015: 46-47 - 2010
- [j1]Chia-Yi Lin, Li-Chung Hsu, Hung-Ming Chen:
On Reducing Test Power, Volume and Routing Cost by Chain Reordering and Test Compression Techniques. IEICE Trans. Electron. 93-C(3): 369-378 (2010)
2000 – 2009
- 2006
- [c1]Li-Chung Hsu, Hung-Ming Chen:
On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design. ISQED 2006: 451-456
Coauthor Index
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