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ORCIDHiroki Yamashita
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2020 – today
- 2023
[c20]Noritaka Ishihara, Yusuke Shimada, Takamitsu Ochi, Satoshi Seto, Haruki Matsuo, Hiroki Yamashita, Sho Morita, Masafumi Ukishima, K. Uejima, Yusuke Arayashiki, Suzuka Kajiwara, Akiyuki Murayama, Katsuya Nishiyama, Kikuko Sugimae, Shinji Mori, Yuta Saito, Takeshi Shundo, Aki Maeda, Hiroyuki Kamiya, Yasuhiro Uchiyama, Makoto Fujiwara, Fumiki Aiso, Katsuyuki Sekine, Norio Ohtani:
Highly Scalable Metal Induced Lateral Crystallization (MILC) Techniques for Vertical Si Channel in Ultra-High (> 300 Layers) 3D Flash Memory. VLSI Technology and Circuits 2023: 1-2- 2020
- [c19]Misato Nihei, Mio Nakamura, Kohei Ikeda, Kazuki Kawamura, Hiroki Yamashita, Minoru Kamata:
Approaching Behavior Analysis for Improving a Mobile Communication Robot in a Nursing Home. HCI (44) 2020: 679-688
2010 – 2019
- 2018
- [j12]Toru Yazaki, Norio Chujo, Takeshi Takemoto, Hiroki Yamashita, Akira Hyogo:
25-Gbps 3-mW/Gbps/ch VCSEL Driver Circuit in 65-nm CMOS for Multichannel Optical Transmitter. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(2): 402-409 (2018) - [j11]Takashi Takemoto
, Yasunobu Matsuoka, Hiroki Yamashita, Yong Lee, Hideo Arimoto, Masaru Kokubo, Tatemi Ido:
A 50-Gb/s High-Sensitivity (-9.2 dBm) Low-Power (7.9 pJ/bit) Optical Receiver Based on 0.18-µm SiGe BiCMOS Technology. IEEE J. Solid State Circuits 53(5): 1518-1538 (2018) - 2017
- [j10]Hiroki Yamashita, Daisuke Sugimura, Takayuki Hamamoto:
Low-light color image enhancement via iterative noise reduction using RGB/NIR sensor. J. Electronic Imaging 26(4): 43017 (2017) - [c18]Hiroki Yamashita, Daisuke Sugimura, Takayuki Hamamoto:
RGB-NIR imaging with exposure bracketing for joint denoising and deblurring of low-light color images. ICASSP 2017: 6055-6059 - 2016
- [j9]Takashi Takemoto, Yasunobu Matsuoka, Hiroki Yamashita, Takahiro Nakamura, Yong Lee, Hideo Arimoto, Tatemi Ido:
A 50-Gb/s Optical Transmitter Based on a 25-Gb/s-Class DFB-LD and a 0.18-µm SiGe BiCMOS LD Driver. IEICE Trans. Electron. 99-C(9): 1039-1047 (2016) - [c17]Takashi Takemoto, Yasunobu Matsuoka, Hiroki Yamashita, Yong Lee, Kenichi Akita, Hideo Arimoto, Masaru Kokubo:
A jitter-reduction packaging structure for a 56-Gb/s NRZ modulated optical receiver. OFC 2016: 1-3 - [c16]Takashi Takemoto, Yasunobu Matsuoka, Hiroki Yamashita, Yong Lee, Kenichi Akita, Hideo Arimoto, Masaru Kokubo, Tatemi Ido:
A 50.6-Gb/s 7.8-mW/Gb/s -7.4-dBm sensitivity optical receiver based on 0.18-µm SiGe BiCMOS technology. VLSI Circuits 2016: 1-2 - 2015
- [j8]Daisuke Sugimura, Takuya Mikami, Hiroki Yamashita, Takayuki Hamamoto:
Enhancing Color Images of Extremely Low Light Scenes Based on RGB/NIR Images Acquisition With Different Exposure Times. IEEE Trans. Image Process. 24(11): 3586-3597 (2015) - [c15]Takashi Takemoto, Hiroki Yamashita, Yasunobu Matsuoka, Yong Lee, Masaru Kokubo:
An electrical and optical concurrent design methodology for enlarging jitter margin of 25.8-Gb/s optical interconnects. CICC 2015: 1-4 - [c14]Takashi Takemoto, Yasunobu Matsuoka, Yoshikazu Sugiyama, Hidenori Yonezawa, Hiroki Yamashita, Koichiro Adachi, Takahiro Nakamura, Etsuko Nomoto, Kouji Nakahara, Hideo Arimoto, Kenichi Osada, Tatemi Ido:
A 50-Gb/s NRZ-modulated optical transmitter based on a DFB-LD and a 0.18-µm SiGe BiCMOS LD driver. OFC 2015: 1-3 - [c13]Hiroki Yamashita, Daisuke Sugimura, Takayuki Hamamoto:
Enhancing low-light color images using an RGB-NIR single sensor. VCIP 2015: 1-4 - 2014
- [j7]Takashi Takemoto, Hiroki Yamashita, Fumio Yuki, Noboru Masuda, Hidehiro Toyoda, Norio Chujo, Yong Lee, Shinji Tsuji, Shinji Nishimura:
A 25-Gb/s 2.2-W 65-nm CMOS Optical Transceiver Using a Power-Supply-Variation-Tolerant Analog Front End and Data-Format Conversion. IEEE J. Solid State Circuits 49(2): 471-485 (2014) - [j6]Takashi Takemoto, Hiroki Yamashita, Toru Yazaki, Norio Chujo, Yong Lee, Yasunobu Matsuoka:
A 25-to-28 Gb/s High-Sensitivity (-9.7 dBm) 65 nm CMOS Optical Receiver for Board-to-Board Interconnects. IEEE J. Solid State Circuits 49(10): 2259-2276 (2014) - [c12]Toru Yazaki, Norio Chujo, Hiroki Yamashita, Takashi Takemoto, Yong Lee, Yasunobu Matsuoka:
25-Gbps×4 optical transmitter with adjustable asymmetric pre-emphasis in 65-nm CMOS. ISCAS 2014: 2692-2695 - 2013
- [c11]Norio Chujo, Takashi Takemoto, Fumio Yuki, Hiroki Yamashita:
High-frequency circuit design for 25 Gb/s×4 optical transceiver. ASP-DAC 2013: 648-651 - [c10]Takashi Takemoto, Hiroki Yamashita, Toru Yazaki, Norio Chujo, Yong Lee, Yasunobu Matsuoka:
A 4× 25-to-28Gb/s 4.9mW/Gb/s -9.7dBm high-sensitivity optical receiver based on 65nm CMOS for board-to-board interconnects. ISSCC 2013: 118-119 - [c9]Norio Chujo, Toru Yazaki, Toshiaki Takai, Daichi Kawamura, Yasunobu Matsuoka, Yong Lee, Toshiki Sugawara, Hiroki Yamashita, Takashi Takemoto, Yoshiaki Ishigami, Kinya Yamazaki, Yoshinori Sunaga, Naoki Matsushima:
A 25-Gb/s × 4-Ch, 8 × 8 mm2, 2.8-mm thick compact optical transceiver module for on-board optical interconnect. OFC/NFOEC 2013: 1-3 - [c8]Takashi Takemoto, Hiroki Yamashita, Fumio Yuki, Shinji Tsuji, Yong Lee, Koichiro Adachi, Kazunori Shinoda, Yasunobu Matsuoka, Toshiki Sugawara, Shinji Nishimura, Norio Chujo, Masaaki Nido, Kazuhiko Kurata, Junji Baba, Yoshinori Watanabe, Naoya Ikeda:
Compact and power-efficient 100-Gbps CMOS-based transceiver. OFC/NFOEC 2013: 1-3 - 2012
- [c7]Takashi Takemoto, Hiroki Yamashita, Takehito Kamimura, Fumio Yuki, Noboru Masuda, Hidehiro Toyoda, Norio Chujo, Kenji Kogo, Yong Lee, Shinji Tsuji, Shinji Nishimura:
A 25-Gb/s 2.2-W optical transceiver using an analog FE tolerant to power supply noise and redundant data format conversion in 65-nm CMOS. VLSIC 2012: 106-107 - 2011
- [j5]Goichi Ono, Keiki Watanabe, Takashi Muto, Hiroki Yamashita, Koji Fukuda, Noboru Masuda, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Fumio Yuki, Masayoshi Yagyu, Hidehiro Toyoda, Masashi Kono, Akihiro Kambe, Seiichi Umai, Tatsuya Saito, Shinji Nishimura:
A 10: 4 MUX and 4: 10 DEMUX Gearbox LSI for 100-Gigabit Ethernet Link. IEEE J. Solid State Circuits 46(12): 3101-3112 (2011) - [c6]Goichi Ono, Keiki Watanabe, Takashi Muto, Hiroki Yamashita, Koji Fukuda, Noboru Masuda, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Fumio Yuki, Masayoshi Yagyu, Hidehiro Toyoda, Akihiro Kambe, Tatsuya Saito, Shinji Nishimura:
10: 4 MUX and 4: 10 DEMUX gearbox LSI for 100-gigabit Ethernet link. ISSCC 2011: 148-150 - 2010
- [j4]Koji Fukuda, Hiroki Yamashita, Goichi Ono, Ryo Nemoto, Eiichi Suzuki, Noboru Masuda, Takashi Takemoto, Fumio Yuki, Tatsuya Saito:
A 12.3-mW 12.5-Gb/s Complete Transceiver in 65-nm CMOS Process. IEEE J. Solid State Circuits 45(12): 2838-2849 (2010) - [c5]Takashi Takemoto, Fumio Yuki, Hiroki Yamashita, Shinji Tsuji, Tatsuya Saito, Shinji Nishimura:
A 25 Gb/s × 4-channel 74 mW/ch transimpedance amplifier in 65 nm CMOS. CICC 2010: 1-4 - [c4]Koji Fukuda, Hiroki Yamashita, Goichi Ono, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Fumio Yuki, Tatsuya Saito:
A 12.3mW 12.5Gb/s complete transceiver in 65nm CMOS. ISSCC 2010: 368-369
2000 – 2009
- 2009
- [j3]Koji Fukuda, Hiroki Yamashita, Fumio Yuki, Goichi Ono, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Masashi Kono, Tatsuya Saito:
A 10-Gb/s Receiver With Track-and-Hold-Type Linear Phase Detector and Charge-Redistribution First-Order ΔΣ Modulator in 90-nm CMOS. IEEE J. Solid State Circuits 44(12): 3539-3546 (2009) - [c3]Koji Fukuda, Hiroki Yamashita, Fumio Yuki, Goichi Ono, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Tatsuya Saito:
10Gb/s receiver with track-and-hold-type linear phase detector and charge-redistribution 1st-order ΔΣ modulator. ISSCC 2009: 186-187 - 2008
- [c2]Koji Fukuda, Hiroki Yamashita, Fumio Yuki, Masayoshi Yagyu, Ryo Nemoto, Takashi Takemoto, Tatsuya Saito, Norio Chujo, Keiichi Yamamoto, Hisaaki Kanai, Atsuhiro Hayashi:
An 8Gb/s Transceiver with 3×-Oversampling 2-Threshold Eye-Tracking CDR Circuit for -36.8dB-loss Backplane. ISSCC 2008: 98-99 - 2006
- [j2]Tatsuya Kawashimo, Hiroki Yamashita, Masayoshi Yagyu, Fumio Yuki:
A Low-Power Write Driver for Hard Disk Drives. IEICE Trans. Electron. 89-C(11): 1670-1673 (2006) - 2005
- [c1]Y. Hayashi, Masahito Sonehara, S. Ueno, Y. Ito, Akio Koyama, Hiroki Yamashita:
A 1.2Gb/s write driver with pre-emphasis overshoot control optimized for high density HDD applications. CICC 2005: 519-522 - 2004
- [j1]Yoshio Miki, Tatsuya Saito, Hiroki Yamashita, Fumio Yuki, Takashige Baba, Akio Koyama, Masahito Sonehara:
A 50-mW/ch 2.5-Gb/s/ch data recovery circuit for the SFI-5 interface with digital eye-tracking. IEEE J. Solid State Circuits 39(4): 613-621 (2004)
Coauthor Index
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