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ORCIDYasuhiro Takashima
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2020 – today
- 2021
[c27]Yasuhiro Takashima, Yuichi Nakamura:
Theoretical and Experimental Analysis of Traveling Salesman Walk Problem. APCCAS 2021: 241-244
2010 – 2019
- 2018
- [c26]Ryota Tsuchihashi, Komei Nomura, Yasuhiro Takashima, Yuichi Nakamura:
Task Allocation and Scheduling Optimization in the Heterogeneous Core System. NGCAS 2018: 86-89 - [c25]Tomohiro Takahashi, Yasuhiro Takashima:
Fast Approximate Algorithm for the Single Source Shortest Path with Lazy Update. NGCAS 2018: 94-97 - 2016
- [j11]Tieyuan Pan, Li Zhu, Lian Zeng, Takahiro Watanabe, Yasuhiro Takashima:
An Online Task Placement Algorithm Based on MER Enumeration for Partially Reconfigurable Device. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(7): 1345-1354 (2016) - [j10]Tieyuan Pan, Lian Zeng, Yasuhiro Takashima, Takahiro Watanabe:
A Fast MER Enumeration Algorithm for Online Task Placement on Reconfigurable FPGAs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(12): 2412-2424 (2016) - [c24]Tomoharu Tanaka, Mark Helm, Tommaso Vali, Ramin Ghodsi, Koichi Kawai, Jae-Kwan Park, Shigekazu Yamada, Feng Pan, Yuichi Einaga, Ali Ghalam, Toru Tanzawa
, Jason Guo, Takaaki Ichikawa, Erwin Yu, Satoru Tamada, Tetsuji Manabe, Jiro Kishimoto, Yoko Oikawa, Yasuhiro Takashima, Hidehiko Kuge, Midori Morooka, Ali Mohammadzadeh, Jong Kang, Jeff Tsai, Emanuele Sirizotti, Eric Lee, Luyen Vu, Yuxing Liu, Hoon Choi, Kwonsu Cheon, Daesik Song, Daniel Shin, Jung Hee Yun, Michele Piccardi, Kim-Fung Chan, Yogesh Luthra, Dheeraj Srinivasan, Srinivasarao Deshmukh, Kalyan Kavalipurapu, Dan Nguyen, Girolamo Gallo, Sumant Ramprasad, Michelle Luo, Qiang Tang, Michele Incarnati, Agostino Macerola, Luigi Pilolli, Luca De Santis, Massimo Rossini, Violante Moschiano, Giovanni Santin, Bernardino Tronca, Hyunseok Lee, Vipul Patel, Ted Pekny, Aaron Yip, Naveen Prabhu, Purval Sule, Trupti Bemalkhedkar, Kiranmayee Upadhyayula, Camila Jaramillo:
7.7 A 768Gb 3b/cell 3D-floating-gate NAND flash memory. ISSCC 2016: 142-144 - [c23]Komei Nomura, Yasuhiro Takashima, Yuichi Nakamura:
PEVaS: Power and execution-time variation-aware scheduling for MPSoC. NEWCAS 2016: 1-4 - [c22]Nobuyuki Yahiro, Bo Liu, Atsushi Nanri, Shigetoshi Nakatake, Yasuhiro Takashima, Gong Chen:
A multi-functional memory unit with PLA-based reconfigurable decoder. ReConFig 2016: 1-7 - 2015
- [j9]Masato Inagi, Yuichi Nakamura, Yasuhiro Takashima, Shin'ichi Wakabayashi:
Inter-FPGA Routing for Partially Time-Multiplexing Inter-FPGA Signals on Multi-FPGA Systems with Various Topologies. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(12): 2572-2583 (2015) - [c21]Yasuhiro Takashima:
Analytical placement for rectilinear blocks. ASP-DAC 2015: 220-225 - 2014
- [c20]Tieyuan Pan, Ran Zhang, Yasuhiro Takashima, Takahiro Watanabe:
A randomized algorithm for the fixed-length routing problem. APCCAS 2014: 711-714 - [c19]Masatsugu Hosoki, Seiya Nagatsuka, Yasuhiro Takashima:
Delay estimation method for correlated net delay variations. APCCAS 2014: 747-750 - 2013
- [j8]Syota Kuwabara, Yukihide Kohira, Yasuhiro Takashima:
An Effective Overlap Removable Objective for Analytical Placement. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(6): 1348-1356 (2013) - [c18]Syota Kuwabara, Yukihide Kohira, Yasuhiro Takashima:
An acceleration method by GPGPU for analytical placement using quasi-Newton method. ASICON 2013: 1-4 - 2012
- [c17]Seiya Nagatsuka, Yasuhiro Takashima:
Sub-path delay estimation for reconvergent path. APCCAS 2012: 675-678 - 2010
- [j7]Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura:
Globally Optimal Time-multiplexing of Inter-FPGA Connections for Multi-FPGA Prototyping Systems. Inf. Media Technol. 5(2): 388-397 (2010) - [j6]Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura:
Globally Optimal Time-multiplexing of Inter-FPGA Connections for Multi-FPGA Prototyping Systems. IPSJ Trans. Syst. LSI Des. Methodol. 3: 81-90 (2010) - [c16]Takanobu Shiki, Yasuhiro Takashima, Yuichi Nakamura:
Delay analysis of sub-path on fabricated chips by several path-delay tests. ISCAS 2010: 1595-1598
2000 – 2009
- 2009
- [c15]Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura:
Globally optimal time-multiplexing in inter-FPGA connections for accelerating multi-FPGA systems. FPL 2009: 212-217 - [c14]Raymond Zeng, Navneet Chalagalla, Dan Chu, Daniel Elmhurst, Matt Goldman, Chris Haid, Atif Huq, Takaaki Ichikawa, Joel Jorgensen, Owen Jungroth, Nishnat Kajla, Ravinder Kajley, Koichi Kawai, Jiro Kishimoto, Ali Madraswala, Tetsuji Manabe, Vikram Mehta, Midori Morooka, Katie Nguyen, Yoko Oikawa, Bharat Pathak, Rod Rozman, Tom Ryan, Andy Sendrowski, William Sheung, Martin Szwarc, Yasuhiro Takashima, Satoru Tamada, Toru Tanzawa, Tomoharu Tanaka, Mase Taub, Darshak Udeshi, Sjigekazu Yamada, Hiroyuki Yokoyama:
A 172mm2 32Gb MLC NAND flash memory in 34nm CMOS. ISSCC 2009: 236-237 - 2008
- [j5]Yuko Hashizume, Yasuhiro Takashima, Yuichi Nakamura:
Post-Silicon Clock-Timing Tuning Based on Statistical Estimation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(9): 2322-2327 (2008) - [j4]Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Atsushi Takahashi:
Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3539-3547 (2008) - [c13]Shuting Li, Tan Yan, Yasuhiro Takashima, Hiroshi Murata:
Fast wire length estimation in obstructive block placement. ICECS 2008: 654-657 - [c12]Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Atsushi Takahashi:
ILP-based optimization of time-multiplexed I/O assignment for multi-FPGA systems. ISCAS 2008: 1800-1803 - 2007
- [j3]Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Yoji Kajitani:
A Performance-Driven Circuit Bipartitioning Method Considering Time-Multiplexed I/Os. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(5): 924-931 (2007) - [j2]Kunihiko Yanagibashi, Yasuhiro Takashima, Yuichi Nakamura:
A Relocation Method for Circuit Modifications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(12): 2743-2751 (2007) - [c11]Tan Yan, Shuting Li, Yasuhiro Takashima, Hiroshi Murata:
A Theoretical Study on Wire Length Estimation Algorithms for Placement with Opaque Blocks. ASP-DAC 2007: 268-273 - 2006
- [j1]Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani:
The Oct-Touched Tile: A New Architecture for Shape-Based Routing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(2): 448-455 (2006) - [c10]Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Yoji Kajitani:
A performance-driven circuit bipartitioning algorithm for multi-FPGA implementation with time-multiplexed I/Os. FPT 2006: 361-364 - [c9]Tan Yan, Qing Dong, Yasuhiro Takashima, Yoji Kajitani:
How does partitioning matter for 3D floorplanning? ACM Great Lakes Symposium on VLSI 2006: 73-78 - 2005
- [c8]Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani:
The oct-touched tile: a new architecture for shape-based routing. ACM Great Lakes Symposium on VLSI 2005: 126-129 - 2004
- [c7]Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani:
Abstraction and optimization of consistent floorplanning with pillar block constraints. ASP-DAC 2004: 19-24 - [c6]Takashi Nojima, Xiaoke Zhu, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani:
Multi-level placement with circuit schema based clustering in analog IC layouts. ASP-DAC 2004: 406-411 - [c5]Takashi Nojima, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani:
A device-level placement with multi-directional convex clustering. ACM Great Lakes Symposium on VLSI 2004: 196-201 - [c4]Keiji Kida, Xiaoke Zhu, Changwen Zhuang, Yasuhiro Takashima, Shigetoshi Nakatake:
A fast algorithm for crosspoint assignment under crosstalk constraints with shielding effects. ISCAS (4) 2004: 489-492 - 2002
- [c3]Yasuhiro Takashima, Akira Kaneko, Shinji Sato, Mineo Kaneko:
Two-dimensional placement method based on divide-and-replacement. APCCAS (2) 2002: 341-346 - 2000
- [c2]Yukiko Kubo, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani:
Self-reforming routing for stochastic search in VLSI interconnection layout. ASP-DAC 2000: 87-92
1990 – 1999
- 1996
- [c1]Yasuhiro Takashima, Atsushi Takahashi, Yoji Kajitani:
Detailed-Routability of FPGAs with Extremal Switch-Block Structures. ED&TC 1996: 160-164
Coauthor Index
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