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ORCIDNoah Hae-Woong Yang
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- affiliation: Texas A&M University, College Station, TX, USA
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2010 – 2019
- 2019
[j5]Ashkan Roshan-Zamir
, Takayuki Iwai, Yang-Hang Fan, Ankur Kumar, Hae-Woong Yang, Lee Sledjeski, John Hamilton, Soumya Chandramouli, Arlo Aude, Samuel Palermo:
A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS. IEEE J. Solid State Circuits 54(3): 672-684 (2019)- 2018
- [c5]Ashkan Roshan-Zamir, Takayuki Iwai, Yang-Hang Fan, Ankur Kumar, Hae-Woong Yang, Lee Sledjeski, John Hamilton, Soumya Chandramouli, Arlo Aude, Samuel Palermo:
A 56 Gb/s PAM4 receiver with low-overhead threshold and edge-based DFE FIR and IIR-tap adaptation in 65nm CMOS. CICC 2018: 1-4 - 2017
- [j4]Ashkan Roshan-Zamir, Osama Elhadidy, Hae-Woong Yang, Samuel Palermo:
A Reconfigurable 16/32 Gb/s Dual-Mode NRZ/PAM4 SerDes in 65-nm CMOS. IEEE J. Solid State Circuits 52(9): 2430-2447 (2017) - [c4]Hae-Woong Yang, Ashkan Roshan-Zamir, Young-Hoon Song, Samuel Palermo:
A low-power dual-mode 20-Gb/s NRZ and 28-Gb/s PAM-4 voltage-mode transmitter. A-SSCC 2017: 261-264 - 2015
- [c3]Osama Elhadidy, Ashkan Roshan-Zamir, Hae-Woong Yang, Samuel Palermo:
A 32 Gb/s 0.55 mW/Gbps PAM4 1-FIR 2-IIR tap DFE receiver in 65-nm CMOS. VLSIC 2015: 224- - 2014
- [j3]Young-Hoon Song, Noah Hae-Woong Yang, Hao Li, Patrick Yin Chiang, Samuel Palermo:
An 8-16 Gb/s, 0.65-1.05 pJ/b, Voltage-Mode Transmitter With Analog Impedance Modulation Equalization and Sub-3 ns Power-State Transitioning. IEEE J. Solid State Circuits 49(11): 2631-2643 (2014) - [c2]Young-Hoon Song, Hae-Woong Yang, Hao Li, Patrick Yin Chiang, Samuel Palermo:
26.5 An 8-to-16Gb/s 0.65-to-1.05pJ/b 2-tap impedance-modulated voltage-mode transmitter with fast power-state transitioning in 65nm CMOS. ISSCC 2014: 446-447 - [c1]Byungho Min, Noah Hae-Woong Yang, Samuel Palermo:
10 Gb/s adaptive receive-side near-end and far-end crosstalk cancellation circuitry. MWSCAS 2014: 77-80 - 2013
- [j2]Young-Hoon Song, Rui Bai, Kangmin Hu, Noah Hae-Woong Yang, Patrick Yin Chiang, Samuel Palermo:
A 0.47-0.66 pJ/bit, 4.8-8 Gb/s I/O Transceiver in 65 nm CMOS. IEEE J. Solid State Circuits 48(5): 1276-1289 (2013) - [j1]Ehsan Zhian Tabasy, Ayman Shafik, Shan Huang, Noah Hae-Woong Yang, Sebastian Hoyos, Samuel Palermo:
A 6-b 1.6-GS/s ADC With Redundant Cycle One-Tap Embedded DFE in 90-nm CMOS. IEEE J. Solid State Circuits 48(8): 1885-1897 (2013)
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