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2020 – today
- 2021
[j7]Marcel Brand
, Michael Witterauf, Éricles Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich:
*-Predictable MPSoC execution of real-time control applications using invasive computing. Concurr. Comput. Pract. Exp. 33(14) (2021)
2010 – 2019
- 2018
- [b2]Alexandru-Petru Tanase, Frank Hannig, Jürgen Teich:
Symbolic Parallelization of Nested Loop Programs. Springer 2018, ISBN 978-3-319-73908-3, pp. I-XII, 1-176 - [j6]Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig:
Symbolic Multi-Level Loop Mapping of Loop Programs for Massively Parallel Processor Arrays. ACM Trans. Embed. Comput. Syst. 17(2): 31:1-31:27 (2018) - [c17]Éricles Sousa, Michael Witterauf, Marcel Brand, Alexandru Tanase, Frank Hannig, Jürgen Teich:
Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study. ASAP 2018: 1-9 - 2017
- [b1]Alexandru Tanase:
Symbolic parallelization of nested loop programs = Symbolische Parallelisierung verschachtelter Schleifenprogramme. University of Erlangen-Nuremberg, Germany, 2017, pp. 1-196 - [j5]Vivek Singh Bhadouria, Alexandru Tanase, Moritz Schmid, Frank Hannig, Jürgen Teich, Dibyendu Ghoshal:
A Novel Image Impulse Noise Removal Algorithm Optimized for Hardware Accelerators. J. Signal Process. Syst. 89(2): 225-242 (2017) - [c16]Marcel Brand, Frank Hannig, Alexandru Tanase, Jürgen Teich:
Efficiency in ILP processing by using orthogonality. ASAP 2017: 207 - [c15]Marcel Brand, Frank Hannig, Alexandru Tanase, Jürgen Teich:
Orthogonal Instruction Processing: An Alternative to Lightweight VLIW Processors. MCSoC 2017: 5-12 - [c14]Éricles Sousa, Arindam Chakraborty, Alexandru Tanase, Frank Hannig, Jürgen Teich:
TCPA editor: A design automation environment for a class of coarse-grained reconfigurable arrays. ReConFig 2017: 1-3 - [c13]Éricles Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich:
A reconfigurable memory architecture for system integration of coarse-grained reconfigurable arrays. ReConFig 2017: 1-8 - 2016
- [j4]Vahid Lari, Andreas Weichslgartner, Alexandru Tanase, Michael Witterauf, Faramarz Khosravi, Jürgen Teich, Jan Heißwolf, Stephanie Friederich, Jürgen Becker:
Providing fault tolerance through invasive computing. it Inf. Technol. 58(6): 309-328 (2016) - [c12]Michael Witterauf, Alexandru Tanase, Frank Hannig, Jürgen Teich:
Modulo scheduling of symbolically tiled loops for tightly coupled processor arrays. ASAP 2016: 58-66 - 2015
- [j3]Vahid Lari, Jürgen Teich, Alexandru Tanase, Michael Witterauf, Faramarz Khosravi, Brett H. Meyer:
Techniques for on-demand structural redundancy for massively parallel processor arrays. J. Syst. Archit. 61(10): 615-627 (2015) - [c11]Vahid Lari, Alexandru Tanase, Jürgen Teich, Michael Witterauf, Faramarz Khosravi, Frank Hannig, Brett H. Meyer:
A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays. AHS 2015: 1-8 - [c10]Michael Witterauf, Alexandru Tanase, Jürgen Teich, Vahid Lari, Andreas Zwinkau, Gregor Snelting:
Adaptive fault tolerance through invasive computing. AHS 2015: 1-8 - [c9]Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig, Vahid Lari:
On-demand fault-tolerant loop processing on massively parallel processor arrays. ASAP 2015: 194-201 - [c8]Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig:
Symbolic loop parallelization for balancing I/O and memory accesses on processor arrays. MEMOCODE 2015: 188-197 - 2014
- [j2]Frank Hannig, Vahid Lari, Srinivas Boppu, Alexandru Tanase, Oliver Reiche:
Invasive Tightly-Coupled Processor Arrays: A Domain-Specific Architecture/Compiler Co-Design Approach. ACM Trans. Embed. Comput. Syst. 13(4s): 133:1-133:29 (2014) - [j1]Jürgen Teich, Alexandru Tanase, Frank Hannig:
Symbolic Mapping of Loop Programs onto Processor Arrays. J. Signal Process. Syst. 77(1-2): 31-59 (2014) - [c7]Moritz Schmid, Alexandru Tanase, Frank Hannig, Jürgen Teich, Vivek Singh Bhadouria, Dibyendu Ghoshal:
Domain-specific augmentations for High-Level Synthesis. ASAP 2014: 173-177 - [c6]Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig:
Symbolic inner loop parallelisation for massively parallel processor arrays. MEMOCODE 2014: 219-228 - [i1]Vahid Lari, Alexandru Tanase, Frank Hannig, Jürgen Teich:
Massively Parallel Processor Architectures for Resource-aware Computing. CoRR abs/1405.2907 (2014) - 2013
- [c5]Jürgen Teich, Alexandru Tanase, Frank Hannig:
Symbolic parallelization of loop programs for massively parallel processor arrays. ASAP 2013: 1-9 - [c4]Éricles Rodrigues Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich:
Accuracy and performance analysis of Harris Corner computation on tightly-coupled processor arrays. DASIP 2013: 88-95 - [c3]Éricles Rodrigues Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich:
A prototype of an adaptive computer vision algorithm on MPSoC architecture. DASIP 2013: 353-354 - [c2]Alexandru Tanase, Vahid Lari, Frank Hannig, Jürgen Teich:
Exploitation of Quality/Throughput Tradeoffs in Image Processing through Invasive Computing. PARCO 2013: 53-62 - [c1]Moritz Schmid, Frank Hannig, Alexandru Tanase, Jürgen Teich:
High-Level Synthesis Revised - Generation of FPGA Accelerators from a Domain-Specific Language using the Polyhedron Model. PARCO 2013: 497-506
Coauthor Index
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