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Daniel Reiser
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2020 – today
- 2024
- [c7]Jianan Wen, Fabian Luis Vargas, Fukun Zhu, Daniel Reiser
, Andrea Baroni, Markus Fritscher, Eduardo Pérez, Marc Reichenbach, Christian Wenger, Milos Krstic:
Cycle-Accurate FPGA Emulation of RRAM Crossbar Array: Efficient Device and Variability Modeling with Energy Consumption Assessment. LATS 2024: 1-6 - 2023
- [c6]Daniel Reiser
, Marc Reichenbach, Tommaso Rizzi, Andrea Baroni, Markus Fritscher, Christian Wenger, Cristian Zambelli, Davide Bertozzi:
Technology-Aware Drift Resilience Analysis of RRAM Crossbar Array Configurations. NEWCAS 2023: 1-5 - 2022
- [c5]Alessandro Milozzi, Daniel Reiser, Andreas Drost, Thomas Neuner, Marc Tornow, Daniele Ielmini:
Thermal switching of TiO2-based RRAM for parameter extraction and neuromorphic engineering. ESSCIRC 2022: 133-136 - 2021
- [c4]Philipp Holzinger, Daniel Reiser
, Tobias Hahn, Marc Reichenbach:
Fast HBM Access with FPGAs: Analysis, Architectures, and Applications. IPDPS Workshops 2021: 152-159 - [c3]Markus Fritscher, Johannes Knödtel, Daniel Reiser
, Maen Mallah, Stefan Pechmann, Dietmar Fey, Marc Reichenbach:
Simulating large neural networks embedding MLC RRAM as weight storage considering device variations. LASCAS 2021: 1-4 - 2020
- [c2]Johannes Knödtel, Markus Fritscher, Daniel Reiser
, Dietmar Fey, Marco Breiling
, Marc Reichenbach:
A Model-to-Circuit Compiler for Evaluation of DNN Accelerators based on Systolic Arrays and Multibit Emerging Memories. MOCAST 2020: 1-6
2010 – 2019
- 2013
- [c1]Ansgar Mondorf, Maria A. Wimmer, Daniel Reiser:
A Framework for Interoperability Testing in Pan-European Public Service Provision. EGOV 2013: 188-199
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last updated on 2024-08-05 20:25 CEST by the dblp team
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