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2020 – today
- 2022
[j3]Rui Xu
, Sheng Ma, Yaohua Wang, Yang Guo, Dongsheng Li, Yuran Qiao:
Heterogeneous Systolic Array Architecture for Compact CNNs Hardware Accelerators. IEEE Trans. Parallel Distributed Syst. 33(11): 2860-2871 (2022)
2010 – 2019
- 2018
- [j2]You Huang, Junzhong Shen, Yuran Qiao, Mei Wen, Chunyuan Zhang:
MALMM: A multi-array architecture for large-scale matrix multiplication on FPGA. IEICE Electron. Express 15(10): 20180286 (2018) - [c6]Junzhong Shen, You Huang, Zelong Wang, Yuran Qiao, Mei Wen, Chunyuan Zhang:
Towards a Uniform Template-based Architecture for Accelerating 2D and 3D CNNs on FPGA. FPGA 2018: 97-106 - [c5]Junzhong Shen, Yuran Qiao, You Huang, Mei Wen, Chunyuan Zhang:
Towards a Multi-array Architecture for Accelerating Large-scale Matrix Multiplication on FPGAs. ISCAS 2018: 1-5 - [i1]Junzhong Shen, Yuran Qiao, You Huang, Mei Wen, Chunyuan Zhang:
Towards a Multi-array Architecture for Accelerating Large-scale Matrix Multiplication on FPGAs. CoRR abs/1803.03790 (2018) - 2017
- [j1]Yuran Qiao, Junzhong Shen, Tao Xiao, Qianming Yang, Mei Wen, Chunyuan Zhang:
FPGA-accelerated deep convolutional neural networks for high throughput and energy efficiency. Concurr. Comput. Pract. Exp. 29(20) (2017) - [c4]Yuran Qiao, Junzhong Shen, Dafei Huang, Qianming Yang, Mei Wen, Chunyuan Zhang:
Optimizing OpenCL Implementation of Deep Convolutional Neural Network on FPGA. NPC 2017: 100-111 - 2015
- [c3]Tao Xiao, Yuran Qiao, Junzhong Shen, Qianming Yang, Mei Wen:
Unified Virtual Memory Support for Deep CNN Accelerator on SoC FPGA. ICA3PP (1) 2015: 64-76 - 2014
- [c2]Dafei Huang, Mei Wen, Changqing Xun, Dong Chen, Xing Cai, Yuran Qiao, Nan Wu, Chunyuan Zhang:
Automated Transformation of GPU-Specific OpenCL Kernels Targeting Performance Portability on Multi-Core/Many-Core CPUs. Euro-Par 2014: 210-221 - 2013
- [c1]Nan Wu, Yuran Qiao, Mei Wen, Chunyuan Zhang:
ACF: Networks-on-Chip Deadlock Recovery with Accurate Detection and Elastic Credit. APPT 2013: 319-333
Coauthor Index
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