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2020 – today
- 2024
[i1]Ken Nakamura, Takayuki Nozaki:
Decoding Algorithm Correcting Single-Insertion Plus Single-Deletion for Non-binary Quantum Codes. CoRR abs/2409.10924 (2024)- 2023
- [j11]Hiroyuki Uzawa, Shuhei Yoshida, Yukou Iinuma, Saki Hatta, Daisuke Kobayashi, Yuya Omori, Yusuke Horishita, Ken Nakamura, Shuichi Takada, Hassan Toorabally, Koyo Nitta
, Koji Yamazaki, Kimikazu Sano:
High-definition technology of AI inference scheme for object detection on edge/terminal. IEICE Electron. Express 20(13): 20232002 (2023) - [j10]Ken Nakamura, Yuya Omori, Daisuke Kobayashi, Koyo Nitta, Kimikazu Sano, Masayuki Sato, Hiroe Iwasaki, Hiroaki Kobayashi:
An Efficient Reference Image Sharing Method for the Image-Division Parallel Video Encoding Architecture. IEICE Trans. Electron. 106(6): 312-320 (2023) - [j9]Daisuke Kobayashi, Ken Nakamura, Masaki Kitahara, Tatsuya Osawa, Yuya Omori, Takayuki Onishi, Hiroe Iwasaki:
A Low-Latency 4K HEVC Multi-Channel Encoding System with Content-Aware Bitrate Control for Live Streaming. IEICE Trans. Inf. Syst. 106(1): 46-57 (2023) - 2022
- [c19]Ken Nakamura, Yuya Omori, Daisuke Kobayashi, Koyo Nitta, Kimikazu Sano, Masayuki Sato, Hiroe Iwasaki, Hiroaki Kobayashi:
An Efficient Reference Image Sharing Method for the Parallel Video Encoding Architecture. COOL CHIPS 2022: 1-3 - [c18]Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Hiroe Iwasaki, Daisuke Kobayashi, Yuya Omori, Ken Nakamura, Koyo Nitta, Kimikazu Sano:
OpenCL-Based Design of an FPGA Accelerator for H.266/VVC Transform and Quantization. MWSCAS 2022: 1-4 - [c17]Masayuki Sato, Yuya Omori, Ryusuke Egawa, Ken Nakamura, Daisuke Kobayashi, Hiroe Iwasaki, Kazuhiko Komatsu, Hiroaki Kobayashi:
A Partitioned Memory Architecture with Prefetching for Efficient Video Encoders. PDCAT 2022: 288-300 - 2021
- [j8]Hiroyuki Uzawa, Shuhei Yoshida, Yuukou Iinuma, Saki Hatta, Daisuke Kobayashi, Yuya Omori, Ken Nakamura, Shuichi Takada, Hassan Toorabally, Kimikazu Sano:
High-definition object detection technology based on AI inference scheme and its implementation. IEICE Electron. Express 18(22): 20210323 (2021) - 2020
- [j7]Ken Nakamura, Daisuke Kobayashi, Yuya Omori, Tatsuya Osawa, Takayuki Onishi, Koyo Nitta, Hiroe Iwasaki:
Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture. IEICE Trans. Electron. 103-C(3): 77-84 (2020) - [c16]Yasuhiro Mochida, Takahiro Yamaguchi, Ken Nakamura:
MMT-based Multi-channel Video Transmission System with Synchronous Processing Architecture. COOL CHIPS 2020: 1-3
2010 – 2019
- 2019
- [c15]Ken Nakamura, Yuya Omori, Daisuke Kobayashi, Tatsuya Osawa, Takayuki Onishi, Koyo Nitta, Hiroe Iwasaki, Atsushi Shimizu:
Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture. COOL CHIPS 2019: 1-3 - [c14]Daisuke Kobayashi, Ken Nakamura, Tatsuya Osawa, Yuya Omori, Takayuki Onishi, Hiroe Iwasaki:
A Real-Time 4K HEVC Multi-Channel Encoding System with Content-Aware Bitrate Control. GLOBECOM 2019: 1-6 - [c13]Yuya Omori, Ken Nakamura, Takayuki Onishi, Daisuke Kobayashi, Tatsuya Osawa, Hiroe Iwasaki:
4K 120fps HEVC Temporal Scalable Encoder with Super Low Delay. ICECS 2019: 410-413 - [c12]Yasuhiro Mochida, Takayuki Nakachi, Takahiro Yamaguchi, Takayuki Onishi, Ken Nakamura:
An MMT Module for 4K/120fps Temporally Scalable Video. ISCAS 2019: 1-5 - [c11]Takayuki Onishi, Yuya Omori, Ken Nakamura, Hiroe Iwasaki, Atsushi Shimizu:
A Low Power Motion Estimation Engine with Adaptive Bit-Shifted SAD Calculation. ISCAS 2019: 1-5 - 2018
- [j6]Daisuke Kobayashi, Ken Nakamura, Takayuki Onishi, Hiroe Iwasaki, Atsushi Shimizu:
A 4K/60p HEVC Real-Time Encoding System With High Quality HDR Color Representations. IEEE Trans. Consumer Electron. 64(4): 433-441 (2018) - [j5]Takayuki Onishi, Takashi Sano, Yukikuni Nishida, Kazuya Yokohari, Ken Nakamura, Koyo Nitta, Kimiko Kawashima, Jun Okamoto, Naoki Ono, Atsushi Sagata, Hiroe Iwasaki, Mitsuo Ikeda, Atsushi Shimizu:
A Single-Chip 4K 60-fps 4: 2: 2 HEVC Video Encoder LSI Employing Efficient Motion Estimation and Mode Decision Framework With Scalability to 8K. IEEE Trans. Very Large Scale Integr. Syst. 26(10): 1930-1938 (2018) - [c10]Daisuke Kobayashi, Ken Nakamura, Takayuki Onishi, Yasuyuki Nakajima, Hiroe Iwasaki, Mitsuo Ikeda, Atsushi Shimizu:
An HEVC real-time encoding system with high quality HDR color representations. ICCE 2018: 1-2 - 2015
- [c9]Hiroe Iwasaki, Takayuki Onishi, Ken Nakamura, Koyo Nitta, Takashi Sano, Yukikuni Nishida, Kazuya Yokohari, Jia Su, Naoki Ono, Ritsu Kusaba, Atsushi Sagata, Mitsuo Ikeda, Atsushi Shimizu:
Professional H.265/HEVC encoder LSI toward high-quality 4K/8K broadcast infrastructure. Hot Chips Symposium 2015: 1-24 - [c8]Takayuki Onishi, Takashi Sano, Yukikuni Nishida, Kazuya Yokohari, Jia Su, Ken Nakamura, Koyo Nitta, Kimiko Kawashima, Jun Okamoto, Naoki Ono, Ritsu Kusaba, Atsushi Sagata, Hiroe Iwasaki, Mitsuo Ikeda, Atsushi Shimizu:
Single-chip 4K 60fps 4: 2: 2 HEVC video encoder LSI with 8K scalability. VLSIC 2015: 54- - 2012
- [j4]Koyo Nitta, Hiroe Iwasaki, Takayuki Onishi, Takashi Sano, Atsushi Sagata, Yasuyuki Nakajima, Minoru Inamori, Ryuichi Tanida, Atsushi Shimizu, Ken Nakamura, Mitsuo Ikeda, Jiro Naganuma:
An H.264/AVC High422 Profile and MPEG-2 422 Profile Encoder LSI for HDTV Broadcasting Infrastructures. IEICE Trans. Electron. 95-C(4): 432-440 (2012)
2000 – 2009
- 2008
- [j3]Takeshi Yoshitome, Ken Nakamura, Jiro Naganuma, Yoshiyuki Yashima:
A Flexible Video CODEC System for Super High Resolution Video. IEICE Trans. Inf. Syst. 91-D(11): 2709-2717 (2008) - [j2]Takayuki Onishi, Ken Nakamura, Takeshi Yoshitome, Jiro Naganuma:
A Distributed Stream Multiplexing Architecture for Multi-Chip Configuration beyond HDTV. IEICE Trans. Inf. Syst. 91-D(12): 2862-2867 (2008) - 2007
- [j1]Hiroe Iwasaki, Jiro Naganuma, Koyo Nitta, Ken Nakamura, Takeshi Yoshitome, Mitsuo Ogura, Yasuyuki Nakajima, Yutaka Tashiro, Takayuki Onishi, Mitsuo Ikeda, Toshihiro Minami, Makoto Endo, Yoshiyuki Yashima:
Single-Chip MPEG-2 422P@HL CODEC LSI With Multichip Configuration for Large Scale Processing Beyond HDTV Level. IEEE Trans. Very Large Scale Integr. Syst. 15(9): 1055-1059 (2007) - 2004
- [c7]Ken Nakamura, Takeshi Yoshitome, Yoshiyuki Yashima:
Super high resolution video codec system with multiple MPEG-s HDTV codec LSI's. ISCAS (3) 2004: 793-796 - 2003
- [c6]Hiroe Iwasaki, Jiro Naganuma, Yasuyuki Nakajima, Yutaka Tashiro, Ken Nakamura, Takeshi Yoshitome, Takayuki Onishi, Mitsuo Ikeda, Takaaki Izuoka, Makoto Endo:
A 1.1 W single-chip MPEG-2 HDTV codec LSI for embedding in consumer-oriented mobile codec systems. CICC 2003: 177-180 - [c5]Hiroe Iwasaki, Jiro Naganuma, Koyo Nitta, Ken Nakamura, Takeshi Yoshitome, Mitsuo Ogura, Yasuyuki Nakajima, Yutaka Tashiro, Takayuki Onishi, Mitsuo Ikeda, Makoto Endo:
Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level. DATE 2003: 20002-20007 - [c4]Takeshi Yoshitome, Ken Nakamura, Yoshiyuki Yashima, Makoto Endo:
Scalable architecture for use in an over-HDTV real-time codec system for multiresolution video. VCIP 2003: 1752-1759 - 2000
- [c3]Ken Nakamura, Mitsuo Ikeda, Takeshi Yoshitome, Takeshi Ogura:
Global Rate Control Scheme for MPEG-2 HDTV Parallel Encoding System. ITCC 2000: 195-200
1990 – 1999
- 1997
- [c2]Noriyuki Matsuda, Ken Nakamura:
Interactive Support for Decision Making. HCI (2) 1997: 479-482 - 1995
- [c1]Ken Nakamura, Kaichi Sagara:
Neuro-aided guidance system for optimum desulphurization treatment in torpedo cars. ICNN 1995: 575-579
Coauthor Index
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