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ORCIDSachhidh Kannan
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2020 – today
- 2023
[j4]Karthikeyan Nagarajan
, Rupshali Roy, Rasit Onur Topaloglu, Sachhidh Kannan, Swaroop Ghosh:
SCANN: Side Channel Analysis of Spiking Neural Networks. Cryptogr. 7(2): 17 (2023)- 2022
- [c7]Karthikeyan Nagarajan, Junde Li, Sina Sayyah Ensan, Mohammad Nasim Imtiaz Khan, Sachhidh Kannan, Swaroop Ghosh:
Analysis of Power-Oriented Fault Injection Attacks on Spiking Neural Networks. DATE 2022: 861-866 - [i1]Karthikeyan Nagarajan, Junde Li, Sina Sayyah Ensan, Mohammad Nasim Imtiaz Khan, Sachhidh Kannan, Swaroop Ghosh:
Analysis of Power-Oriented Fault Injection Attacks on Spiking Neural Networks. CoRR abs/2204.04768 (2022)
2010 – 2019
- 2015
- [j3]Sachhidh Kannan, Naghmeh Karimi, Ozgur Sinanoglu, Ramesh Karri:
Security Vulnerabilities of Emerging Nonvolatile Main Memories and Countermeasures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(1): 2-15 (2015) - [j2]Sachhidh Kannan, Naghmeh Karimi, Ramesh Karri, Ozgur Sinanoglu:
Modeling, Detection, and Diagnosis of Faults in Multilevel Memristor Memories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(5): 822-834 (2015) - 2014
- [c6]Sachhidh Kannan, Naghmeh Karimi, Ozgur Sinanoglu:
Secure Memristor-based Main Memory. DAC 2014: 178:1-178:6 - [c5]Sachhidh Kannan, Naghmeh Karimi, Ramesh Karri, Ozgur Sinanoglu:
Detection, diagnosis, and repair of faults in memristor-based memories. VTS 2014: 1-6 - 2013
- [c4]Sachhidh Kannan, Ramesh Karri, Ozgur Sinanoglu:
Sneak path testing and fault modeling for multilevel memristor-based memories. ICCD 2013: 215-220 - [c3]Sachhidh Kannan, Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu:
Sneak-path Testing of Memristor-based Memories. VLSI Design 2013: 386-391 - 2012
- [c2]Sachhidh Kannan, Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu:
Engineering crossbar based emerging memory technologies. ICCD 2012: 478-479 - 2011
- [j1]Aamir Zia, Sachhidh Kannan, H. Jonathan Chao, Garrett S. Rose:
3D NOC for many-core processors. Microelectron. J. 42(12): 1380-1390 (2011) - [c1]Sachhidh Kannan, Garrett S. Rose:
A hierarchical 3-D floorplanning algorithm for many-core CMP networks. ISCAS 2011: 1211-1214
Coauthor Index
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