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ORCIDJinil Chung
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2020 – today
- 2021
[j5]Hyunsu Park, Jincheol Sim, Yoonjae Choi
, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Gyutae Park, Jinil Chung, Kyeong-Min Kim, Hae-Kang Jung, Hyungsoo Kim, Junhyun Chun, Chulwoo Kim:
A 1.3-4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line. IEEE J. Solid State Circuits 56(6): 1886-1896 (2021)- 2020
- [j4]Jinil Chung, Woong Choi, Jongsun Park, Swaroop Ghosh:
Domain Wall Memory-Based Design of Deep Neural Network Convolutional Layers. IEEE Access 8: 19783-19798 (2020)
2010 – 2019
- 2019
- [c4]Dongkyun Kim, Minsu Park, Sungchun Jang, Jun-Yong Song, Hankyu Chi, Geunho Choi, Sunmyung Choi, Jaeil Kim, Changhyun Kim, Kyung Whan Kim, Kibong Koo, Seonghwi Song, Yongmi Kim, Dong-Uk Lee, Jaejin Lee, Dae Suk Kim, Ki Hun Kwon, Minsik Han, Byeongchan Choi, Hongjung Kim, Sanghyun Ku, Yeonuk Kim, Jong-Sam Kim, Sanghui Kim, Youngsuk Seo, Seungwook Oh, Dain Im, Haksong Kim, Jonghyuck Choi, Jinil Chung, Changhyun Lee, Yongsung Lee, Joo-Hwan Cho, Junhyun Chun, Jonghoon Oh:
A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme. ISSCC 2019: 380-382 - 2018
- [c3]Ki Chul Chun, Yonggyu Chu, Jin-Seok Heo, Tae-Sung Kim, Soohwan Kim, Hui-Kap Yang, Mi-Jo Kim, Chang-Kyo Lee, Ju-Hwan Kim, Hyunchul Yoon, Chang-Ho Shin, Sang-uhn Cha, Hyung-Jin Kim, Young-Sik Kim, Kyungryun Kim, Young-Ju Kim, Won-Jun Choi, Daesik Yim, Inkyu Moon, Young-Ju Kim, Junha Lee, Young Choi, Yongmin Kwon, Sung-Won Choi, Jung-Wook Kim, Yoon-Suk Park, Woongdae Kang, Jinil Chung, Seunghyun Kim, Yesin Ryu, Seong-Jin Cho, Hoon Shin, Hangyun Jung, Sanghyuk Kwon, Kyuchang Kang, Jongmyung Lee, Yujung Song, Youngjae Kim, Eun-Ah Kim, Kyung-Soo Ha, Kyoung-Ho Kim, Seok-Hun Hyun, Seung-Bum Ko, Jung-Hwan Choi, Young-Soo Sohn, Kwang-Il Park, Seong-Jin Jang:
A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process. ISSCC 2018: 206-208 - 2016
- [j3]Swaroop Ghosh, Anirudh Iyengar, Seyedhamidreza Motaman, Rekha Govindaraj, Jae-Won Jang, Jinil Chung, Jongsun Park, Xin Li, Rajiv V. Joshi, Dinesh Somasekhar:
Overview of Circuits, Systems, and Applications of Spintronics. IEEE J. Emerg. Sel. Topics Circuits Syst. 6(3): 265-278 (2016) - [j2]Jinil Chung, Kenneth Ramclam, Jongsun Park, Swaroop Ghosh:
Exploiting Serial Access and Asymmetric Read/Write of Domain Wall Memory for Area and Energy-Efficient Digital Signal Processor Design. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(1): 91-102 (2016) - [c2]Jinil Chung, Jongsun Park, Swaroop Ghosh:
Domain Wall Memory based Convolutional Neural Networks for Bit-width Extendability and Energy-Efficiency. ISLPED 2016: 332-337 - 2015
- [c1]Jinil Chung, Kenneth Ramclam, Jongsun Park, Swaroop Ghosh:
Domain wall memory based digital signal processors for area and energy-efficiency. DAC 2015: 64:1-64:6 - 2014
- [j1]Bongsub Song, Kyunghoon Kim, Junan Lee, Jinil Chung, Youngjung Choi, Jinwook Burm:
A 13.5-mW 10-Gb/s 4-PAM Serial Link Transmitter in 0.13-µm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs 61-II(9): 646-650 (2014)
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