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2020 – today
- 2023
[c8]Tai-Hao Wen, Je-Min Hung, Hung-Hsi Hsu, Yuan Wu, Fu-Chun Chang, Chung-Yuan Li, Chih-Han Chien, Chin-I Su, Win-San Khwa, Jui-Jen Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Mon-Shu Ho, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang:
A 28nm Nonvolatile AI Edge Processor using 4Mb Analog-Based Near-Memory-Compute ReRAM with 27.2 TOPS/W for Tiny AI Edge Devices. VLSI Technology and Circuits 2023: 1-2
2010 – 2019
- 2019
- [c7]Kea-Tiong Tang, Wei-Chen Wei, Zuo-Wei Yeh, Tzu-Hsiang Hsu, Yen-Cheng Chiu, Cheng-Xin Xue, Yu-Chun Kuo, Tai-Hsing Wen, Mon-Shu Ho, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Meng-Fan Chang:
Considerations Of Integrating Computing-In-Memory And Processing-In-Sensor Into Convolutional Neural Network Accelerators For Low-Power Edge Devices. VLSI Circuits 2019: 166- - 2018
- [c6]Yixiong Yang, Zhibo Wang, Pei Yang, Meng-Fan Chang, Mon-Shu Ho, Huazhong Yang, Yongpan Liu:
A 2-GHz Direct Digital Frequency Synthesizer Based on LUT and Rotation. ISCAS 2018: 1-5 - 2017
- [c5]Chunmeng Dou, Wei-Hao Chen, Yi-Ju Chen, Huan-Ting Lin, Wei-Yu Lin, Mon-Shu Ho, Meng-Fan Chang:
Challenges of emerging memory and memristor based circuits: Nonvolatile logics, IoT security, deep learning and neuromorphic computing. ASICON 2017: 140-143 - 2015
- [c4]Meng-Fan Chang, Albert Lee, Chien-Chen Lin, Mon-Shu Ho, Ping-Cheng Chen, Chia-Chen Kuo, Ming-Pin Chen, Pei-Ling Tseng, Tzu-Kun Ku, Chien-Fu Chen
, Kai-Shin Li, Jia-Min Shieh:
Read circuits for resistive memory (ReRAM) and memristor-based nonvolatile Logics. ASP-DAC 2015: 569-574 - [c3]Albert Lee, Meng-Fan Chang, Chien-Chen Lin, Chien-Fu Chen, Mon-Shu Ho, Chia-Chen Kuo, Pei-Ling Tseng, Shyh-Shyuan Sheu, Tzu-Kun Ku:
RRAM-based 7T1R nonvolatile SRAM with 2x reduction in store energy and 94x reduction in restore energy for frequent-off instant-on applications. VLSIC 2015: 76- - 2014
- [c2]Meng-Fan Chang, Che-Wei Wu, Jui-Yu Hung, Ya-Chin King, Chomg-Jung Lin, Mon-Shu Ho, Chia-Cheng Kuo, Shyh-Shyuan Sheu:
A low-power subthreshold-to-superthreshold level-shifter for sub-0.5V embedded resistive RAM (ReRAM) macro in ultra low-voltage chips. APCCAS 2014: 695-698 - 2012
- [c1]Ming-Pin Chen, Lai-Fu Chen, Meng-Fan Chang, Shu-Meng Yang, Yao-Jen Kuo, Jui-Jen Wu, Mon-Shu Ho, Hsiu-Yun Su, Yuan-Hua Chu, Wen-Chin Wu, Tzu-Yi Yang, Hiroyuki Yamauchi:
A 260mV L-shaped 7T SRAM with bit-line (BL) Swing expansion schemes based on boosted BL, asymmetric-VTH read-port, and offset cell VDD biasing techniques. VLSIC 2012: 112-113
Coauthor Index
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