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ORCIDRyuta Kawano
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2020 – today
- 2022
[j6]Yoshiya Shikama
, Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, Yusuke Nagasaka, Naoto Fukumoto, Michihiro Koibuchi:
A traffic-aware memory-cube network using bypassing. Microprocess. Microsystems 90: 104471 (2022)- [c11]Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Dynamic Routing Reconfiguration for Low-Latency and Deadlock-Free Interconnection Networks. CANDAR 2022: 117-123 - 2021
- [c10]Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
GPU Parallelization of All-Pairs-Shortest-Path Algorithm in Low-Degree Unweighted Regular Graph. ACIT 2021: 51-55 - [c9]Yoshiya Shikama, Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, Yusuke Nagasaka, Naoto Fukumoto, Michihiro Koibuchi:
Low-Latency Low-Energy Memory-Cube Networks using Dual-Voltage Datapaths. PDP 2021: 143-147 - 2020
- [j5]Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
A Generalized Theory Based on the Turn Model for Deadlock-Free Irregular Networks. IEICE Trans. Inf. Syst. 103-D(1): 101-110 (2020) - [j4]Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Traffic-Independent Multi-Path Routing for High-Throughput Data Center Networks. IEICE Trans. Inf. Syst. 103-D(12): 2471-2479 (2020) - [c8]Ryuta Kawano, Hiroki Matsutani, Hideharu Amano:
Layout-Oriented Low-Diameter Topology for HPC Interconnection Networks. CANDAR (Workshops) 2020: 93-99
2010 – 2019
- 2019
- [c7]Ryuta Kawano, Hiroki Matsutani, Hideharu Amano:
Deadlock-Free Layered Routing for Infiniband Networks. CANDAR Workshops 2019: 84-90 - 2018
- [c6]Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Hideharu Amano:
k-Optimized Path Routing for High-Throughput Data Center Networks. CANDAR 2018: 99-105 - 2017
- [j3]Ryuta Kawano, Hiroshi Nakahara, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
A Novel Channel Assignment Method to Ensure Deadlock-Freedom for Deterministic Routing. IEICE Trans. Inf. Syst. 100-D(8): 1798-1806 (2017) - [j2]Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
A Layout-Oriented Routing Method for Low-Latency HPC Networks. IEICE Trans. Inf. Syst. 100-D(12): 2796-2807 (2017) - [j1]Yusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Ryuta Kawano, Hideharu Amano:
Body Bias Domain Partitioning Size Exploration for a Coarse Grained Reconfigurable Accelerator. IEICE Trans. Inf. Syst. 100-D(12): 2828-2836 (2017) - [c5]Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
HiRy: An Advanced Theory on Design of Deadlock-Free Adaptive Routing for Arbitrary Topologies. ICPADS 2017: 664-673 - 2016
- [c4]Ryuta Kawano, Hiroshi Nakahara, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
ACRO: Assignment of channels in reverse order to make arbitrary routing deadlock-free. ICIS 2016: 1-6 - [c3]Yusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Ryuta Kawano, Hideharu Amano:
Body bias grain size exploration for a coarse grained reconfigurable accelerator. FPL 2016: 1-4 - [c2]Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
LOREN: A Scalable Routing Method for Layout-Conscious Random Topologies. CANDAR 2016: 9-18 - 2015
- [c1]Ryuta Kawano, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi:
Optimized Core-Links for Low-Latency NoCs. PDP 2015: 172-176
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