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ORCIDMingche Lai
This is just a disambiguation page, and is not intended to be the bibliography of an actual person. Any publication listed on this page has not been assigned to an actual author yet. If you know the true author of one of the publications listed below, you are welcome to contact us.
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2020 – today
- 2024
[j24]Xiaoyue Hu, Fangxu Lv, Mingche Lai, Zhang Luo, Qiang Wang, Chaolong Xu, Ruotian Yin, Zhouhao Yang, Cewen Liu:
A high speed and low BER dual-mode adaptive equalizer using hybrid parallel DFE. IEICE Electron. Express 21(19): 20240417 (2024)- [j23]Bolin Ren
, Fangxu Lv, Mingche Lai, Liquan Xiao, Geng Zhang, Xuqiang Zheng, Zhang Luo, Jiaqing Xu:
A 56-Gb/s,0.708 pJ/bit single-ended simultaneous bidirectional transceiver with hybrid errors cancellation techniques for die-to-die interface. Microelectron. J. 152: 106326 (2024) - [j22]Meng Li, Fangxu Lv, Mingche Lai, Xuqiang Zheng, Heng Huang, Xingyun Qi, Geng Zhang:
A fully digital timing background calibration algorithm based on first-order auto-correlation for time-interleaved ADCs. Microelectron. J. 152: 106330 (2024) - [j21]Zhang Luo, Sichun Du, Zedi Zhang, Fangxu Lv, Qinghui Hong, Mingche Lai:
Artificial Neural Network Based on Memristive Circuit for High-Speed Equalization. IEEE Trans. Circuits Syst. I Regul. Pap. 71(4): 1745-1756 (2024) - [j20]Kewei Xin, Mingche Lai, Fangxu Lv, Xuqiang Zheng, Kaile Guo, Zhengbin Pang, Chaolong Xu, Geng Zhang, Wenchen Wang, Meng Li:
Frequency Domain Modeling and Performance Analysis of Injection-Locked LC Oscillator. IEEE Trans. Circuits Syst. II Express Briefs 71(1): 11-15 (2024) - [c35]Yu He, Xuqiang Zhenq, Zedong Wang, Zunsong Yanq, Hua Xu, Fangxu Lv, Mingche Lai, Xinyu Liu:
An Injection-Locked Clock Multiplier with Adaptive Pulsewidth Adjustment and Phase Error Cancellation Achieving 43.9fs RMS Jitter and -255.5dB FoM. CICC 2024: 1-2 - [c34]Yuxuan Qin, Chuxiong Lin, Mingche Lai, Zhang Luo, Shi Xu, Weifeng He:
Reducing DRAM Latency via In-situ Temperature- and Process-Variation-Aware Timing Detection and Adaption. DAC 2024: 67:1-67:6 - [c33]Haoyu Liao, Yuan Li, Puguang Liu, Qiang Wang, Mingche Lai, Xingyun Qi:
Optimization of TDM Using Single-ended Transmission for Multi-FPGA Platforms. ISCAS 2024: 1-5 - [i1]Yanjing Wang, Lizhou Wu, Wentao Hong, Yang Ou, Zicong Wang, Sunfeng Gao, Jie Zhang, Sheng Ma, Dezun Dong, Xingyun Qi, Mingche Lai, Nong Xiao:
A Comprehensive Simulation Framework for CXL Disaggregated Memory. CoRR abs/2411.02282 (2024) - 2023
- [j19]Qiuyue Zhang, Xuqiang Zheng, Fangxu Lv, Zhaoyang Liu, Hua Xu, Weijie Li, Zhi Jin, Mingche Lai, Xinyu Liu:
A 50 Gb/s PAM-4 EAM driver in 28-nm CMOS technology. Microelectron. J. 140: 105905 (2023) - [j18]Bingxi Pei, Shi Xu, Zhang Luo, Qin Wang, Mingche Lai, Weifeng He:
A Unified Clock-Gated Error Correction Scheme With Three-Phase Latch-Based Pipeline for Energy-Efficient Wide Supply Voltage Range Router. IEEE Trans. Circuits Syst. II Express Briefs 70(10): 3787-3791 (2023) - [c32]Mingche Lai, Fangxu Lv, Geng Zhang, Chaolong Xu:
A Low BER Cooperative-adaptive-equalizer for Serial Receiver in HPC Networks. HPCC/DSS/SmartCity/DependSys 2023: 742-749 - [c31]Lin Shao, Mingche Lai, Shi Xu, Chuxiong Lin, Weifeng He:
A Metastability Inference and Avoidance Technique for Near-Threshold-Voltage Network-on-Chip. ISCAS 2023: 1-5 - 2022
- [j17]Geng Zhang, Mingche Lai, Fangxu Lyu, Xuqiang Zheng, Heming Wang, Dongbin Lv, Chaolong Xu, Xingyun Qi, Qing Liu:
A CNRZ-7 Based Wireline Transceiver With High-Bandwidth-Density, Low-Power for D2D Communication. IEEE Access 10: 96556-96567 (2022) - [j16]Bingxi Pei, Shi Xu, Zhang Luo, Qin Wang, Mingche Lai, Wei-Feng He:
Hierarchical photoelectric hybrid packet switching network for high-performance computing. JOCN 14(8): 680-690 (2022) - [j15]Mingche Lai, Geng Zhang, Fangxu Lv, Xuqiang Zheng, Heming Wang, Dongbin Lv, Chaolong Xu, Xingyun Qi:
A 33.33 Gb/s/wire pin-efficient 1.06 pJ/bit wireline transceiver based on CNRZ-5 for Chiplet in 28 nm CMOS. Microelectron. J. 130: 105628 (2022) - [c30]Jijun Cao, Mingche Lai, Lu Liu, Jiaqing Xu, Xiaoyue Hu:
In-Band Management Framework and Performance Evaluation for Interconnect Network in the TianHe Exascale Prototype System. HPCC/DSS/SmartCity/DependSys 2022: 438-445 - [c29]Xuran Ge, Ming-che Lai, Yang Liu, Lizhou Wu, Zhutao Zhuang, Yang Ou, Zhiguang Chen, Nong Xiao:
SpacKV: A Pmem-Aware Key-Value Separation Store Based on LSM-Tree. NPC 2022: 327-339 - 2021
- [c28]Xingyun Qi, Mingche Lai, Dezun Dong, Yi Dai, Junsheng Chang, Jijun Cao:
PFT: A Congestion Avoidance Method based on Proactive Flow Throttling at Endpoints. IM 2021: 572-578 - 2020
- [j14]Shi Xu, Mingche Lai, Yi Dai, Jijun Cao, Kefei Wang:
A scalable smart router architecture with intelligent adaptive routing and fault-tolerant management. Neurocomputing 393: 126-141 (2020) - [c27]Jijun Cao, Mingche Lai, Xingyun Qi, Yi Dai, Zhengbin Pang:
Optimal Implementation of In-Band Network Management for High-Radix Switches. ACA 2020: 16-30 - [c26]Zhengbin Pang, Fangxu Lv, Weiping Tang, Mingche Lai, Kaile Guo, Yuxuan Wu, Tao Liu, Miaomiao Wu, Dechao Lu:
A 32 Gb/s Low Power Little Area Re-timer with PI Based CDR in 65 nm CMOS Technology. ACA 2020: 31-42 - [c25]Xingyun Qi, Pingjing Lu, Jijun Cao, Yi Dai, Mingche Lai, Junsheng Chang:
MPLEG: A Multi-mode Physical Layer Error Generator for Link Layer Fault Tolerance Test. ACA 2020: 56-69 - [c24]Chao Wang, Weixia Xu, Mingche Lai, Jijun Cao:
Design of Converged Network Coding Layer for the Ethernet and HPC High-Speed Network. HPCC/DSS/SmartCity 2020: 163-169
2010 – 2019
- 2019
- [c23]Yi Dai, Ke Wu, Mingche Lai, Qiong Li, Dezun Dong:
PPS: A Low-Latency and Low-Complexity Switching Architecture Based on Packet Prefetch and Arbitration Prediction. ICA3PP (1) 2019: 3-16 - [c22]Jijun Cao, Mingche Lai, Zhang Luo, Jiaqing Xu, Zhengbin Pang:
Efficient Management and Intelligent Fault Tolerance for HPC Interconnect Networks. ICPADS 2019: 343-351 - 2018
- [j13]Jie Jian, Mingche Lai, Liquan Xiao:
Optimize the Power Consumption and SNR of the 3D Photonic High-Radix Switch Architecture Based on Extra Channels and Redundant Rings. J. Comput. Networks Commun. 2018: 8074074:1-8074074:8 (2018) - [j12]Shi Xu, Zhang Luo, Mingche Lai, Zhengbin Pang, Renfa Li:
Integrated High-Speed Optical SerDes over 100GBd Based on Optical Time Division Multiplexing. ACM J. Emerg. Technol. Comput. Syst. 14(2): 27:1-27:16 (2018) - [j11]Xiangke Liao, Kai Lu, Canqun Yang, Jin-wen Li, Yuan Yuan, Ming-che Lai, Libo Huang, Pingjing Lu, Jianbin Fang, Jing Ren, Jie Shen:
Moving from exascale to zettascale computing: challenges and techniques. Frontiers Inf. Technol. Electron. Eng. 19(10): 1236-1244 (2018) - 2016
- [j10]Jie Jian, Mingche Lai, Liquan Xiao:
A Fast Hierarchical Arbitration in Optical Network-on-Chip Based on Multi-Level Priority QoS. IEICE Trans. Commun. 99-B(4): 875-884 (2016) - [c21]Jie Jian, Mingche Lai, Liquan Xiao, Weixia Xu:
Graphein: A Novel Optical High-Radix Switch Architecture for 3D Integration. ICA3PP 2016: 162-177 - [c20]Jie Jian, Liquan Xiao, Mingche Lai, Shi Xu:
A High-Radix Switch Architecture Based on Silicon Photonic and 3D Integration. NCCET 2016: 179-190 - 2015
- [c19]Jie Jian, Mingche Lai, Liquan Xiao:
A Low-Latency and High-Throughput Multiple-Level Arbitration Scheme Supporting Quality-of-Service in Optical On-chip Network. NoCArc@MICRO 2015: 9-14 - 2014
- [j9]Sheng Ma, Natalie D. Enright Jerger, Zhiying Wang, Ming-che Lai, Libo Huang:
Holistic Routing Algorithm Design to Support Workload Consolidation in NoCs. IEEE Trans. Computers 63(3): 529-542 (2014) - 2013
- [j8]Ming-che Lai, Lei Gao, Nong Xiao, Zhiying Wang:
An accurate and highly-efficient performance evaluation approach based on queuing model for on-chip network. Sci. China Inf. Sci. 56(7): 1-20 (2013) - [j7]Libo Huang, Nong Xiao, Zhiying Wang, Yongwen Wang, Ming-che Lai:
Efficient multimedia coprocessor with enhanced SIMD engines for exploiting ILP and DLP. Parallel Comput. 39(10): 586-602 (2013) - [c18]Lei Gao, Ming-che Lai, Kefei Wang, Zhengbin Pang:
A Highly-Efficient Approach to Adaptive Load Balance for Scalable TBGP. NCCET 2013: 101-110 - 2011
- [j6]Nong Xiao, Zhiguang Chen, Fang Liu, Ming-che Lai, Longfei An:
P3Stor: A parallel, durable flash-based SSD for enterprise-scale storage systems. Sci. China Inf. Sci. 54(6): 1129-1141 (2011) - [j5]Ming-che Lai, Lei Gao:
Two-level tries: A general acceleration structure for parallel routing table accesses. J. Commun. Networks 13(4): 408-417 (2011) - [j4]Ming-che Lai, Lei Gao, Sheng Ma, Nong Xiao, Zhiying Wang:
A practical low-latency router architecture with wing channel for on-chip network. Microprocess. Microsystems 35(2): 98-109 (2011) - [c17]Yang Ou, Nong Xiao, Ming-che Lai:
A Scalable Multi-channel Parallel NAND Flash Memory Controller Architecture. ChinaGrid 2011: 48-53 - 2010
- [j3]Ming-Che Lai, Hansuk Sohn, Tzu-Liang (Bill) Tseng, Chunkuan Chiang:
A hybrid algorithm for capacitated plant location problem. Expert Syst. Appl. 37(12): 8599-8605 (2010) - [j2]Ming-che Lai, Lei Gao, Zhiying Wang:
Exploration and implementation of a highly efficient processor element for multimedia and signal processing domains. IET Comput. Digit. Tech. 4(5): 374-387 (2010)
2000 – 2009
- 2009
- [c16]Ming-che Lai, Lei Gao, Nong Xiao, Zhiying Wang:
An accurate and efficient performance analysis approach based on queuing model for network on chip. ICCAD 2009: 563-570 - [c15]Lei Gao, Ming-che Lai, Zhenghu Gong:
An Improved Parallel Access Technology on Routing Table for Threaded BGP. ICPADS 2009: 198-204 - [c14]Gao Lai, Ming-che Lai, Zhenghu Gong:
A Practical Non-blocking Route Propagation Technology for Threaded BGP. ScalCom-EmbeddedCom 2009: 206-211 - 2008
- [j1]Lei Gao, Zhenghu Gong, Yaping Liu, Ming-che Lai, Wei Peng:
A TLP approach for BGP based on local speculation. Sci. China Ser. F Inf. Sci. 51(11): 1772-1784 (2008) - [c13]Jianjun Guo, Ming-che Lai, Zhengyuan Pang, Libo Huang, Fangyuan Chen, Kui Dai, Zhiying Wang:
Memory System Design for a Multi-core Processor. CISIS 2008: 601-606 - [c12]Ming-che Lai, Jianjun Guo, Zhuxi Zhang, Zhiying Wang:
Using an Automated Approach to Explore and Design a High-Efficiency Processor Element for the Multimedia Domain. CISIS 2008: 613-618 - [c11]Ming-che Lai, Lei Gao, Wei Shi, Zhiying Wang:
Escaping from Blocking: A Dynamic Virtual Channel for Pipelined Routers. CISIS 2008: 795-800 - [c10]Lei Gao, Ming-che Lai, Zhenghu Gong:
Exploiting the Thread-Level Parallelism for BGP on Multi-core. CNSR 2008: 510-516 - [c9]Ming-che Lai, Zhiying Wang, Lei Gao, Hongyi Lu, Kui Dai:
A dynamically-allocated virtual channel architecture with congestion awareness for on-chip routers. DAC 2008: 630-633 - [c8]Jianjun Guo, Kui Dai, Ming-che Lai, Zhiying Wang:
The P2P Communication Model for a Local Memory based Multi-core Processor. ICYCS 2008: 1354-1359 - [c7]Jianjun Guo, Ming-che Lai, Zhengyuan Pang, Libo Huang, Fangyuan Chen, Kui Dai, Zhiying Wang:
Hierarchical memory system design for a heterogeneous multi-core processor. SAC 2008: 1504-1508 - 2007
- [c6]Ming-che Lai, Jianjun Guo, Lv Yasuai, Kui Dai, Zhiying Wang:
The Research of an Embedded Processor Element for Multimedia Domain. MCAM 2007: 267-276 - [c5]Libo Huang, Ming-che Lai, Kui Dai, Hong Yue, Li Shen:
Hardware Support for Arithmetic Units of Processor with Multimedia Extension. MUE 2007: 633-637 - [c4]Ming-che Lai, Zhiying Wang, Jianjun Guo, Kui Dai, Shen Li:
Template Vertical Dictionary-Based Program Compression Scheme on the TTA. PATMOS 2007: 43-52 - 2006
- [c3]Ming-che Lai, Kui Dai, Lu Hong-yi, Zhiying Wang:
A Novel Data-Parallel Coprocessor for Multimedia Signal Processing. ICME 2006: 369-372 - 2005
- [c2]Hong Yue, Ming-che Lai, Kui Dai, Zhiying Wang:
Design of a Configurable Embedded Processor Architecture for DSP Functions. ICPADS (2) 2005: 27-31 - 2004
- [c1]Ming-che Lai, Kui Dai, Li Shen, Zhiying Wang:
A New Technique for Program Code Compression in Embedded Microprocessor. ICESS 2004: 158-164
Coauthor Index
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