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ORCIDA. E. A. Almaini
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2010 – 2019
- 2014
[j12]Meng Yang, Jinmei Lai, A. E. A. Almaini:
An Architecture Independent Packing Method for LUT-based Commercial FPGA. J. Comput. 9(5): 1131-1137 (2014)- 2013
- [c7]Meng Yang, Jiarong Tong, A. E. A. Almaini:
Indirect connection aware attraction for FPGA clustering (abstract only). FPGA 2013: 265 - 2011
- [j11]B. A. Al Jassani, Neil Urquhart, A. E. A. Almaini:
State assignment for sequential circuits using multi-objective genetic algorithm. IET Comput. Digit. Tech. 5(4): 296-305 (2011) - [j10]Lun-Yao Wang, Yinshui Xia, Xiexiong Chen, A. E. A. Almaini:
Reed-Muller function optimization techniques with onset table. J. Zhejiang Univ. Sci. C 12(4): 288-296 (2011) - 2010
- [j9]B. A. Al Jassani, Neil Urquhart, A. E. A. Almaini:
Manipulation and optimisation techniques for Boolean logic. IET Comput. Digit. Tech. 4(3): 227-239 (2010)
2000 – 2009
- 2008
- [j8]Meng Yang, Lingli Wang, Jiarong Tong, A. E. A. Almaini:
Techniques for dual forms of Reed-Muller expansion conversion. Integr. 41(1): 113-122 (2008) - 2006
- [c6]Meng Yang, Lingli Wang, A. E. A. Almaini:
Fast Conversion for Large Canonical OR-Coincidence Functions. APCCAS 2006: 1643-1646 - 2005
- [j7]Yinshui Xia, Lun-Yao Wang, A. E. A. Almaini:
A Novel Multiple-Valued CMOS Flip-Flop Employing Multiple-Valued Clock. J. Comput. Sci. Technol. 20(2): 237-242 (2005) - 2004
- [j6]B. Ali, A. E. A. Almaini, Tatiana Kalganova
:
Evolutionary Algorithms and Theirs Use in the Design of Sequential Logic Circuits. Genet. Program. Evolvable Mach. 5(1): 11-29 (2004) - 2003
- [j5]M. MacCallum, A. E. A. Almaini:
The Application of the Wavelet Transform to Polysomnographic Signals. Int. J. Wavelets Multiresolution Inf. Process. 1(3): 263-274 (2003) - [j4]Yinshui Xia, Xunwei Wu, A. E. A. Almaini:
Power Minimization of FPRM Functions Based on Polarity Conversion. J. Comput. Sci. Technol. 18(3): 325-331 (2003) - [c5]Yinshui Xia, B. Ali, A. E. A. Almaini:
Area and power optimization of FPRM function based circuits. ISCAS (5) 2003: 329-332 - 2002
- [c4]Yinshui Xia, A. E. A. Almaini:
Best Polarity for Low Power XOR Gate Decomposition. DSD 2002: 53-59 - 2001
- [c3]Lingli Wang, A. E. A. Almaini:
Multilevel Logic Minimization Using Functional Don't Cares. VLSI Design 2001: 417-424 - [c2]M. MacCallum, A. E. A. Almaini:
The Application of the Wavelet Transform to Polysomnographic Signals. WAA 2001: 284-295
1990 – 1999
- 1994
- [c1]Z. Guan, P. Thomson, A. E. A. Almaini:
A Parallel CMOS 2's Complement Multiplier Based on 5: 3 Counter. ICCD 1994: 298-301 - 1990
- [j3]A. E. A. Almaini, S. S. Aziz:
ASIC implementation of a programmable error-trapping decoder for binary codes of length 15. Microprocess. Microsystems 14(4): 256-262 (1990) - [j2]A. E. A. Almaini:
An introduction to microcomputer systems architecture and interfacing: Fulcher, J Addison-Wesley, Workingham, UK (1989) pp 425. Microprocess. Microsystems 14(9): 615 (1990)
1970 – 1979
- 1978
- [j1]A. E. A. Almaini:
Sequential Machine Implementations Using Universal Logic Modules. IEEE Trans. Computers 27(10): 951-960 (1978)
Coauthor Index
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