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ORCIDMikhail Asiatici
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2020 – today
- 2022
[j5]Mikhail Asiatici
, Paolo Ienne:
Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs. ACM Trans. Reconfigurable Technol. Syst. 15(2): 13:1-13:33 (2022)- 2021
- [b1]Mikhail Asiatici:
Miss-Optimized Memory Systems: Turning Thousands of Outstanding Misses into Reuse Opportunities. EPFL, Switzerland, 2021 - [j4]Mikhail Asiatici, Damian Maiorano, Paolo Ienne:
How Many CPU Cores is an FPGA Worth? Lessons Learned from Accelerating String Sorting on a CPU-FPGA System. J. Signal Process. Syst. 93(12): 1405-1417 (2021) - [c8]Mikhail Asiatici, Paolo Ienne:
Large-Scale Graph Processing on FPGAs with Caches for Thousands of Simultaneous Misses. ISCA 2021: 609-622 - 2020
- [c7]Mikhail Asiatici, Damian Maiorano, Paolo Ienne:
FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort. ASAP 2020: 133-140
2010 – 2019
- 2019
- [j3]Andrea Guerrieri, Sahand Kashani-Akhavan, Mikhail Asiatici, Paolo Ienne:
Snap-On User-Space Manager for Dynamically Reconfigurable System-on-Chips. IEEE Access 7: 103938-103947 (2019) - [c6]Mikhail Asiatici, Paolo Ienne:
Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of Outstanding Misses in FPGAs. FPGA 2019: 310-319 - [c5]Mikhail Asiatici, Paolo Ienne:
DynaBurst: Dynamically Assemblying DRAM Bursts over a Multitude of Random Accesses. FPL 2019: 254-262 - [c4]Gabor Csordas, Mikhail Asiatici, Paolo Ienne:
In Search of Lost Bandwidth: Extensive Reordering of DRAM Accesses on FPGA. FPT 2019: 188-196 - 2018
- [j2]Miku J. Laakso, Simon J. Bleiker, Jessica Liljeholm, Gustaf E. Martensson, Mikhail Asiatici, Andreas C. Fischer, Göran Stemme, Thorbjorn Ebefors, Frank Niklaus:
Through-Glass Vias for Glass Interposers and MEMS Packaging Applications Fabricated Using Magnetic Assembly of Microscale Metal Wires. IEEE Access 6: 44306-44317 (2018) - [c3]Mikhail Asiatici, Damian Maiorano, Paolo Ienne:
FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort (pHS5)(Abstract Only). FPGA 2018: 294 - [c2]Andrea Guerrieri, Sahand Kashani-Akhavan, Mikhail Asiatici, Pasquale Lombardi, Bilel Belhadj, Paolo Ienne:
LEOSoC: An Open-Source Cross-Platform Embedded Linux Library for Managing Hardware Accelerators in Heterogeneous System-on-Chips(Abstract Only). FPGA 2018: 295 - 2017
- [j1]Mikhail Asiatici, Nithin George, Kizheppatt Vipin, Suhaib A. Fahmy, Paolo Ienne:
Virtualized Execution Runtime for FPGA Accelerators in the Cloud. IEEE Access 5: 1900-1910 (2017) - 2016
- [c1]Mikhail Asiatici, Nithin George, Kizheppatt Vipin, Suhaib A. Fahmy, Paolo Ienne:
Designing a virtual runtime for FPGA accelerators in the cloud. FPL 2016: 1-2
Coauthor Index
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