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Kaijie Wei
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2020 – today
- 2024
- [c14]Kaijie Wei
, Hideharu Amano
, Ryohei Niwase
, Yoshiki Yamaguchi
:
A data compressor for FPGA-based state vector quantum simulators. HEART 2024: 63-70 - 2023
- [j4]Kaijie Wei, Yuki Kuno, Masatoshi Arai, Hideharu Amano:
RT-libSGM: FPGA-Oriented Real-Time Stereo Matching System with High Scalability. IEICE Trans. Inf. Syst. 106(3): 337-348 (2023) - [c13]Ziquan Qin, Kaijie Wei, Hideharu Amano, Kazuhiro Nakadai:
Low power implementation of Geometric High-order Decorrelation-based Source Separation on an FPGA board. COOL CHIPS 2023: 1-6 - [c12]Kaijie Wei, Ryohei Niwase, Hideharu Amano, Yoshiki Yamaguchi, Takefumi Miyoshi:
A state vector quantum simulator working on FPGAs with extensible SATA storage. ICFPT 2023: 272-273 - [c11]Ryohei Niwase, Hikaru Harasawa, Yoshiki Yamaguchi, Kaijie Wei, Hideharu Amano, Takefumi Miyoshi:
Enormous-Scale Quantum State Vector Calculation with FPGA-accelerated SATA storages. ICFPT 2023: 288-289 - [c10]Ryohei Niwase, Hikaru Harasawa, Yoshiki Yamaguchi, Kaijie Wei, Hideharu Amano:
A cost/power efficient storage system with directly connected FPGA and SATA disks. MCSoC 2023: 51-58 - 2022
- [j3]Renzhi Mao, Kaijie Wei, Hideharu Amano, Yuki Kuno, Masatoshi Arai:
Weighted Least Square Filter for Improving the Quality of Depth Map on FPGA. Int. J. Netw. Comput. 12(2): 425-445 (2022) - [c9]Kaijie Wei, Yuki Kuno, Masatoshi Arai, Hideharu Amano:
RT-libSGM: An Implementation of a Real-time Stereo Matching System on FPGA. HEART 2022: 1-9 - [c8]Yuchen Chen, Kaijie Wei, Hiroaki Nishi
, Hideharu Amano:
An Implementation of a 3D Image Filter for Motion Vector Generation on an FPGA Board. CANDAR 2022: 83-89 - [c7]Zhongyang Hou, Kaijie Wei, Hideharu Amano, Kazuhiro Nakadai:
An FPGA off-loading of HARK sound source localization. CANDARW 2022: 236-240 - [c6]Pengyu Huang, Kaijie Wei, Hideharu Amano, Kaori Ohkoda, Masashi Aono:
Multi-board FPGA Implementation to Solve the Satisfiability Problem for Multi-Agent Path Finding in Smart Factory. CANDARW 2022: 406-410 - 2021
- [j2]Koki Honda, Kaijie Wei
, Masatoshi Arai, Hideharu Amano:
CLAHE Implementation and Evaluation on a Low-End FPGA Board by High-Level Synthesis. IEICE Trans. Inf. Syst. 104-D(12): 2048-2056 (2021) - [j1]Kaijie Wei, Koki Honda, Hideharu Amano:
An implementation methodology for Neural Network on a Low-end FPGA Board. Int. J. Netw. Comput. 11(2): 172-197 (2021) - [c5]Renzhi Mao, Kaijie Wei
, Hideharu Amano, Yuki Kuno, Masatoshi Arai:
Weight Least Square Filter for Improving the Quality of Depth Map on FPGA. CANDAR (Workshops) 2021: 297-300 - 2020
- [c4]Kaijie Wei
, Koki Honda, Hideharu Amano:
An implementation methodology for Neural Network on a Low-end FPGA Board. CANDAR 2020: 228-234 - [c3]Koki Honda, Kaijie Wei
, Masatoshi Arai, Hideharu Amano:
CLAHE implementation on a low-end FPGA board by high-level synthesis. CANDAR (Workshops) 2020: 282-285
2010 – 2019
- 2019
- [c2]Koki Honda, Kaijie Wei
, Hideharu Amano:
FPGA/Python Co-Design for Lane Line Detection on a PYNQ-Z1 Board. MCSoC 2019: 53-60 - 2018
- [c1]Kaijie Wei
, Koki Honda, Hideharu Amano:
FPGA Design for Autonomous Vehicle Driving Using Binarized Neural Networks. FPT 2018: 425-428
Coauthor Index
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last updated on 2024-07-05 20:18 CEST by the dblp team
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