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2020 – today
- 2024
[c31]Soyed Tuhin Ahmed, Kamal Danouchi, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori:
Enhancing Reliability of Neural Networks at the Edge: Inverted Normalization with Stochastic Affine Transformations. DATE 2024: 1-6- [c30]Soyed Tuhin Ahmed, Kamal Danouchi, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori:
NeuSpin: Design of a Reliable Edge Neuromorphic System Based on Spintronics for Green AI. DATE 2024: 1-6 - [c29]Soyed Tuhin Ahmed
, Kamal Danouchi, Michael Hefenbrock, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori:
Testing Spintronics Implemented Monte Carlo Dropout-Based Bayesian Neural Networks. ETS 2024: 1-6 - [i6]Soyed Tuhin Ahmed, Michael Hefenbrock, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori:
Testing Spintronics Implemented Monte Carlo Dropout-Based Bayesian Neural Networks. CoRR abs/2401.04744 (2024) - [i5]Soyed Tuhin Ahmed, Kamal Danouchi, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori:
NeuSpin: Design of a Reliable Edge Neuromorphic System Based on Spintronics for Green AI. CoRR abs/2401.06195 (2024) - [i4]Soyed Tuhin Ahmed, Kamal Danouchi, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori:
Enhancing Reliability of Neural Networks at the Edge: Inverted Normalization with Stochastic Affine Transformations. CoRR abs/2401.12416 (2024) - 2023
- [j10]Soyed Tuhin Ahmed, Kamal Danouchi, Christopher Münch, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori:
SpinDrop: Dropout-Based Bayesian Binary Neural Networks With Spintronic Implementation. IEEE J. Emerg. Sel. Topics Circuits Syst. 13(1): 150-164 (2023) - [j9]Ghislain Takam Tchendjou, Kamal Danouchi, Guillaume Prenat, Lorena Anghel:
Spintronic Memristor-Based Binarized Ensemble Convolutional Neural Network Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(6): 1885-1897 (2023) - [j8]Soyed Tuhin Ahmed, Kamal Danouchi, Michael Hefenbrock, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori:
SpinBayes: Algorithm-Hardware Co-Design for Uncertainty Estimation Using Bayesian In-Memory Approximation on Spintronic-Based Architectures. ACM Trans. Embed. Comput. Syst. 22(5s): 131:1-131:25 (2023) - [c28]Soyed Tuhin Ahmed, Kamal Danouchi, Michael Hefenbrock, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori:
Scalable Spintronics-based Bayesian Neural Network for Uncertainty Estimation. DATE 2023: 1-6 - [c27]Kamal Danouchi, Guillaume Prenat, Philippe Talatchian, Louis Hutin, Lorena Anghel:
Robustness and Power Efficiency in Spin-Orbit Torque-Based Probabilistic Logic Circuits. ISVLSI 2023: 1-6 - [i3]Joao Henrique Quintino Palhares, Yann Beilliard, Jury Sandrini, Franck Arnaud, Kevin Garello, Guillaume Prenat, Lorena Anghel, Fabien Alibart, Dominique Drouin, Philippe Galy:
A tunable and versatile 28nm FD-SOI crossbar output circuit for low power analog SNN inference with eNVM synapses. CoRR abs/2305.16187 (2023) - [i2]Soyed Tuhin Ahmed, Kamal Danouchi, Michael Hefenbrock, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori:
Spatial-SpinDrop: Spatial Dropout-based Binary Bayesian Neural Network with Spintronics Implementation. CoRR abs/2306.10185 (2023) - [i1]Soyed Tuhin Ahmed, Kamal Danouchi, Michael Hefenbrock, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori:
Scale-Dropout: Estimating Uncertainty in Deep Neural Networks Using Stochastic Scale. CoRR abs/2311.15816 (2023) - 2022
- [j7]Etienne Becle, Guillaume Prenat, Philippe Talatchian, Lorena Anghel, Ioan Lucian Prejbeanu:
A Fast, Energy Efficient and Tunable Magnetic Tunnel Junction Based Bitstream Generator for Stochastic Computing. IEEE Trans. Circuits Syst. I Regul. Pap. 69(8): 3251-3259 (2022) - [c26]Kamal Danouchi, Guillaume Prenat, Lorena Anghel:
Spin Orbit Torque-based Crossbar Array for Error Resilient Binary Convolutional Neural Network. LATS 2022: 1-6 - [c25]Soyed Tuhin Ahmed, Kamal Danouchi, Christopher Münch, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori:
Binary Bayesian Neural Networks for Efficient Uncertainty Estimation Leveraging Inherent Stochasticity of Spintronic Devices. NANOARCH 2022: 11:1-11:6 - [c24]Theo Soriano, David Novo, Guillaume Prenat, Gregory di Pendina, Pascal Benoit:
MemCork: Exploration of Hybrid Memory Architectures for Intermittent Computing at the Edge. VLSI-SoC 2022: 1-6 - 2021
- [c23]Etienne Becle, Philippe Talatchian, Guillaume Prenat, Lorena Anghel, Ioan Lucian Prejbeanu:
Fast Behavioral VerilogA Compact Model for Stochastic MTJ. ESSDERC 2021: 259-262 - 2020
- [c22]Mehdi Baradaran Tahoori, Sarath Mohanachandran Nair, Rajendra Bishnoi, Lionel Torres, Sophiane Senni, Guillaume Patrigeon, Pascal Benoit, Gregory di Pendina, Guillaume Prenat:
A Universal Spintronic Technology based on Multifunctional Standardized Stack. DATE 2020: 394-399
2010 – 2019
- 2019
- [j6]Guillaume Patrigeon, Pascal Benoit, Lionel Torres, Sophiane Senni, Guillaume Prenat, Gregory di Pendina:
Design and Evaluation of a 28-nm FD-SOI STT-MRAM for Ultra-Low Power Microcontrollers. IEEE Access 7: 58085-58093 (2019) - 2018
- [c21]Mehdi Baradaran Tahoori, Sarath Mohanachandran Nair, Rajendra Bishnoi, Sophiane Senni, Jad Mohdad, Frédérick Mailly, Lionel Torres, Pascal Benoit, Abdoulaye Gamatié, Pascal Nouet, Frederic Ouattara, Gilles Sassatelli, Kotb Jabeur, Pierre Vanhauwaert, A. Atitoaie, I. Firastrau, Gregory di Pendina, Guillaume Prenat:
Using multifunctional standardized stack as universal spintronic technology for IoT. DATE 2018: 931-936 - [c20]Mounia Kharbouche-Harrari, Rana Alhalabi, Jérémy Postel-Pellerin, Romain Wacquez, Driss Aboulkassimi, Etienne Nowak, Ioan Lucian Prejbeanu, Guillaume Prenat, Gregory di Pendina:
MRAM: from STT to SOT, for security and memory. DCIS 2018: 1-6 - [c19]Elena-Ioana Vatajelu, Lorena Anghel, Jean-Michel Portal, Marc Bocquet, Guillaume Prenat:
Resistive and Spintronic RAMs: Device, Simulation, and Applications. IOLTS 2018: 109-114 - [c18]Sophiane Senni, Frederic Ouattara, Jad Mohdad, Kaan Sevin, Guillaume Patrigeon, Pascal Benoit, Pascal Nouet, Lionel Torres, François Duhem, Gregory di Pendina, Guillaume Prenat:
From Spintronic Devices to Hybrid CMOS/Magnetic System On Chip. VLSI-SoC 2018: 188-191 - 2017
- [c17]Mehdi Baradaran Tahoori, Sarath Mohanachandran Nair, Rajendra Bishnoi, Sophiane Senni, Jad Mohdad, Frédérick Mailly, Lionel Torres, Pascal Benoit, Pascal Nouet, Rui Ma, Martin Kreißig, Frank Ellinger, Kotb Jabeur, Pierre Vanhauwaert, Gregory di Pendina, Guillaume Prenat:
GREAT: HeteroGeneous IntegRated Magnetic tEchnology Using Multifunctional Standardized sTack. ISVLSI 2017: 344-349 - 2016
- [j5]Christophe Layer, Laurent Becker, Kotb Jabeur, Sylvain Claireux, Bernard Dieny, Guillaume Prenat, Gregory di Pendina, Stephane Gros, Pierre Paoli, Virgile Javerliac, Fabrice Bernard-Granger, Loïc Decloedt:
Reducing System Power Consumption Using Check-Pointing on Nonvolatile Embedded Magnetic Random Access Memories. ACM J. Emerg. Technol. Comput. Syst. 12(4): 32:1-32:24 (2016) - [j4]Guillaume Prenat, Kotb Jabeur, Pierre Vanhauwaert, Gregory di Pendina, Fabian Oboril, Rajendra Bishnoi, Mojtaba Ebrahimi, Nathalie Lamard, Olivier Boulle, Kevin Garello, Juergen Langer, Berthold Ocker, Marie Claire Cyrille, Pietro Gambardella, Mehdi Baradaran Tahoori, Gilles Gaudin:
Ultra-Fast and High-Reliability SOT-MRAM: From Cache Replacement to Normally-Off Computing. IEEE Trans. Multi Scale Comput. Syst. 2(1): 49-60 (2016) - [c16]Erya Deng, Lorena Anghel, Guillaume Prenat, Weisheng Zhao:
Multi-context non-volatile content addressable memory using magnetic tunnel junctions. NANOARCH 2016: 103-108 - 2015
- [j3]Erya Deng, Yue Zhang, Wang Kang, Bernard Dieny, Jacques-Olivier Klein, Guillaume Prenat, Weisheng Zhao:
Synchronous 8-bit Non-Volatile Full-Adder based on Spin Transfer Torque Magnetic Tunnel Junction. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(7): 1757-1765 (2015) - [c15]Erya Deng, You Wang, Zhaohao Wang, Jacques-Olivier Klein, Bernard Dieny, Guillaume Prenat, Weisheng Zhao:
Robust magnetic full-adder with voltage sensing 2T/2MTJ cell. NANOARCH 2015: 27-32 - 2014
- [c14]Gregory di Pendina, Kotb Jabeur, Guillaume Prenat:
Hybrid CMOS/magnetic Process Design Kit and SOT-based non-volatile standard cell architectures. ASP-DAC 2014: 692-699 - [c13]Guillaume Prenat, Gregory di Pendina, Christophe Layer, Olivier Goncalves, K. Jaber, Bernard Dieny, Ricardo C. Sousa, Ioan Lucian Prejbeanu, Jean-Pierre Nozieres:
Magnetic memories: From DRAM replacement to ultra low power logic chips. DATE 2014: 1 - [c12]Gregory di Pendina, Guillaume Prenat, Bernard Dieny:
InMRAM: Introductory course on Magnetic Random Access Memories for microelectronics students and engineers. EWME 2014: 21-25 - 2013
- [c11]Olivier Goncalves, Guillaume Prenat, Gregory di Pendina, Bernard Dieny:
Non-volatile FPGAs based on spintronic devices. DAC 2013: 126:1-126:3 - [c10]Weisheng Zhao, Guillaume Prenat, Jacques-Olivier Klein, Bernard Dieny, Claude Chappert, Dafine Ravelosona:
Emerging hybrid logic circuits based on non-volatile magnetic memories. NEWCAS 2013: 1-4 - 2012
- [c9]Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Guillaume Prenat, Jérémy Alvarez-Herault, Ken Mackay:
Impact of Resistive-Bridge Defects in TAS-MRAM Architectures. Asian Test Symposium 2012: 125-130 - [c8]Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Guillaume Prenat, Jérémy Alvarez-Herault, Ken Mackay:
Impact of resistive-open defects on the heat current of TAS-MRAM architectures. DATE 2012: 532-537 - [c7]Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Guillaume Prenat, Jérémy Alvarez-Herault, Ken Mackay:
Coupling-based resistive-open defects in TAS-MRAM architectures. ETS 2012: 1 - 2011
- [c6]Guillaume Prenat, Bernard Dieny, Jean-Pierre Nozieres, Gregory di Pendina, Kholdoun Torki:
Hybrid CMOS/Magnetic Process Design Kit and application to the design of high-performances non-volatile logic circuits. ICCAD 2011: 240-245 - [c5]Gregory di Pendina, Kholdoun Torki, Guillaume Prenat, Yoann Guillemenet, Lionel Torres:
Ultra Compact Non-volatile Flip-Flop for Low Power Digital Circuits Based on Hybrid CMOS/Magnetic Technology. PATMOS 2011: 83-91
2000 – 2009
- 2009
- [j2]Weisheng Zhao, Eric Belhaire, Claude Chappert, Bernard Dieny, Guillaume Prenat:
TAS-MRAM-Based Low-Power High-Speed Runtime Reconfiguration (RTR) FPGA. ACM Trans. Reconfigurable Technol. Syst. 2(2): 8:1-8:19 (2009) - 2007
- [c4]Weisheng Zhao, Eric Belhaire, Bernard Dieny, Guillaume Prenat, Claude Chappert:
TAS-MRAM based Non-volatile FPGA logic circuit. FPT 2007: 153-160 - [c3]Guillaume Prenat, Mourad El Baraji, Wei Guo, Ricardo Sousa, Liliana Buda-Prejbeanu, Bernard Dieny, Virgile Javerliac, Jean-Pierre Nozieres, Weisheng Zhao, Eric Belhaire:
CMOS/Magnetic Hybrid Architectures. ICECS 2007: 190-193 - 2005
- [j1]Guillaume Prenat, Salvador Mir, Diego Vázquez, Luís Rolíndez:
A low-cost digital frequency testing approach for mixed-signal devices using SigmaDelta modulation. Microelectron. J. 36(12): 1080-1090 (2005) - [c2]Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Th. Haniotakis, Guillaume Prenat, Salvador Mir:
A built-in IDDQ testing circuit. ESSCIRC 2005: 471-474 - 2004
- [c1]Luís Rolíndez, Salvador Mir, Guillaume Prenat, Ahcène Bounceur:
A 0.18 µm CMOS Implementation of On-chip Analogue Test Signal Generation from Digital Test Patterns. DATE 2004: 706-707
Coauthor Index
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