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ORCIDJae-Gon Lee
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2020 – today
- 2023
[j7]Jae-Gon Lee
, Younsik Choi, Hoyeon Jeon, Jong-Jin Lee, Dongsuk Shin:
Fully Automated Hardware-Driven Clock-Gating Architecture With Complete Clock Coverage for 4 nm Exynos Mobile SOC. IEEE J. Solid State Circuits 58(1): 90-101 (2023)- 2022
- [j6]Hailin Zeng, Jeong-Hyun Park, Mincheol Kim, Jae-Gon Lee:
Design of EM Sensor for Non-Contact Detection of Defective Wire Harness in Conveyor System. Sensors 22(19): 7350 (2022) - [c9]Jae-Gon Lee, Hoyeon Jeon, Younsik Choi, Ahchan Kim:
Fully Automated Hardware-Driven Clock-Gating Architecture with Complete Clock Coverage for 5nm Exynos Mobile SoC. ISSCC 2022: 216-218 - [c8]Won Suk Lee, Yusheng Bian, Thomas Weeks, Michal Rakowski, Francis O. Afzal, Takako Hirokawa, Asif Chowdhury, Rod Augur, Jae-Gon Lee, Alexander Martin, Ken Giewont:
Automatic Waveguide Balancing Using Point Set Operations. OFC 2022: 1-3 - 2021
- [j5]Jeong-Hyun Park, Jae-Gon Lee:
Low-profile high efficiency transmitarray antenna using optimized phase compensation surface (PCS) and PEC sidewalls. ICT Express 7(4): 501-506 (2021)
2010 – 2019
- 2019
- [c7]Jinook Song, Yunkyo Cho, Jun-Seok Park, Jun-Woo Jang, Sehwan Lee, Joon-Ho Song, Jae-Gon Lee, Inyup Kang:
An 11.5TOPS/W 1024-MAC Butterfly Structure Dual-Core Sparsity-Aware Neural Processing Unit in 8nm Flagship Mobile SoC. ISSCC 2019: 130-132 - 2018
- [j4]Jae-Gon Lee, Taek-Sun Kwon, Bo-Hee Choi, Jeong-Hae Lee:
Compact Controlled Reception Pattern Antenna (CRPA) Array Based on Mu-Zero Resonance (MZR) Antenna. IEICE Trans. Commun. 101-B(6): 1427-1433 (2018) - [j3]Kwi Seob Um, Jae-Gon Lee, Jeong-Hae Lee:
Multiband Antenna Based on Meta-Structured Transmission Line for RF Harvesting Application. IEICE Trans. Commun. 101-B(7): 1701-1707 (2018) - [j2]Jae-Gon Lee, Taek-Sun Kwon, Jeong-Hae Lee:
Effects of Finite Superstrate and Asymmetrical Ground on High Gain Superstrate Antenna. IEICE Trans. Commun. 101-B(8): 1884-1890 (2018) - 2014
- [c6]Tuck-Boon Chan, Kwangsoo Han, Andrew B. Kahng, Jae-Gon Lee, Siddhartha Nath:
OCV-aware top-level clock tree optimization. ACM Great Lakes Symposium on VLSI 2014: 33-38
2000 – 2009
- 2007
- [i1]Jae-Gon Lee, Moo-Kyoung Chung, Ki-Yong Ahn, Sang-Heon Lee, Chong-Min Kyung:
A Prediction Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-Emulation. CoRR abs/0710.4701 (2007) - 2006
- [j1]Jae-Gon Lee, Chong-Min Kyung:
PrePack: Predictive Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-Emulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 1935-1949 (2006) - 2005
- [c5]Jae-Gon Lee, Woo-Seung Yang, Young-Su Kwon, Young-Il Kim, Chong-Min Kyung:
Simulation acceleration of transaction-level models for SoC with RTL sub-blocks. ASP-DAC 2005: 499-502 - [c4]Jae-Gon Lee, Moo-Kyoung Chung, Ki-Yong Ahn, Sang-Heon Lee, Chong-Min Kyung:
A Prediction Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-Emulation. DATE 2005: 384-389 - [c3]Jae-Gon Lee, Ki-Yong Ahn, Chong-Min Kyung:
Predictive Synchronization Scheme between Simulator And Accelerator Free from Performance Deterioration. SoC 2005: 100-103 - 2004
- [c2]Young-Il Kim, Bong-Il Park, Jae-Gon Lee, Chong-Min Kyung:
SmartGlue: an interface controller with auto reconfiguration for field programmable computing machine. ASP-DAC 2004: 734-736 - [c1]Young-Su Kwon, Jae-Gon Lee, Chong-Min Kyung:
Bandwidth tracing arbitration algorithm for mixed-clock SoC with dynamic priority adaptation. ASP-DAC 2004: 806-811
Coauthor Index
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