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ORCIDU. Fat Chio
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2020 – today
- 2020
[j16]Chua-Chin Wang
, Zong-You Hou, Yu-Lin Deng, U. Fat Chio, Wei Wang:
2-GHz 2×VDD 28-nm CMOS Digital Output Buffer with Slew Rate Auto-Adjustment Against Process and Voltage Variations. J. Circuits Syst. Comput. 29(6): 2050088:1-2050088:17 (2020)- [j15]Wen-Liang Zeng, Edoardo Bonizzoni, Chi-Wa U, Chi-Seng Lam, Sai-Weng Sin, U. Fat Chio, Franco Maloberti, Rui Paulo Martins:
A SAR-ADC-Assisted DC-DC Buck Converter With Fast Transient Recovery. IEEE Trans. Circuits Syst. II Express Briefs 67-II(9): 1669-1673 (2020) - [j14]Ji-Xuan Li, Sai-Weng Sin, U. Fat Chio, Ya-Jie Wu, Chi-Seng Lam, Rui Paulo Martins:
Digital Battery Management Unit With Built-In Resistance Compensation, Modulated Frequency Detection and Multi-Mode Protection for Fast, Efficient and Safe Charging. IEEE Trans. Circuits Syst. 67-I(11): 4063-4074 (2020)
2010 – 2019
- 2019
- [j13]U-Fat Chio, Kuo-Chih Wen, Sai-Weng Sin, Chi-Seng Lam, Yan Lu, Franco Maloberti, Rui Paulo Martins:
An Integrated DC-DC Converter With Segmented Frequency Modulation and Multiphase Co-Work Control for Fast Transient Recovery. IEEE J. Solid State Circuits 54(10): 2637-2648 (2019) - [j12]Tzung-Je Lee, Tsung-Yi Tsai, Wei Lin, U. Fat Chio, Chua-Chin Wang:
A Slew Rate Variation Compensated 2× VDD I/O Buffer Using Deterministic P/N-PVT Variation Detection Method. IEEE Trans. Circuits Syst. II Express Briefs 66-II(1): 116-120 (2019) - 2018
- [c20]U. Fat Chio, Kuo-Chih Wen, Sai-Weng Sin, Chi-Seng Lam, Yan Lu, Franco Maloberti, Rui Paulo Martins:
An Integrated DC-DC Converter with Segmented Frequency Modulation and Multiphase Co-Work Control for Fast Transient Recovery. A-SSCC 2018: 31-32 - 2017
- [j11]Tzung-Je Lee, Tsung-Yi Tsai, Wei Lin, U-Fat Chio, Chua-Chin Wang:
A Dynamic Leakage and Slew Rate Compensation Circuit for 40-nm CMOS Mixed-Voltage Output Buffer. IEEE Trans. Very Large Scale Integr. Syst. 25(11): 3166-3174 (2017) - [c19]U. Fat Chio, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, Rui Paulo Martins:
A 5-bit 2 GS/s binary-search ADC with charge-steering comparators. A-SSCC 2017: 221-224 - 2016
- [c18]Dante Gabriel Muratore, Alper Akdikmen, Edoardo Bonizzoni, Franco Maloberti, U. Fat Chio, Sai-Weng Sin, Rui Paulo Martins:
An 8-bit 0.7-GS/s single channel flash-SAR ADC in 65-nm CMOS technology. ESSCIRC 2016: 421-424 - 2014
- [j10]Yan Zhu, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Franco Maloberti:
Split-SAR ADCs: Improved Linearity With Power and Speed Optimization. IEEE Trans. Very Large Scale Integr. Syst. 22(2): 372-383 (2014) - 2013
- [j9]Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
A 2.3 mW 10-bit 170 MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. IEEE J. Solid State Circuits 48(8): 1783-1794 (2013) - [c17]Wen-Lan Wu, Yan Zhu, Li Ding, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins:
A 0.6V 8b 100MS/s SAR ADC with minimized DAC capacitance and switching energy in 65nm CMOS. ISCAS 2013: 2239-2242 - 2012
- [j8]He Gong Wei, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti:
An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC. IEEE J. Solid State Circuits 47(11): 2763-2772 (2012) - [c16]Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins:
A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC. CICC 2012: 1-4 - [c15]Rui Wang, U-Fat Chio, Sai-Weng Sin, Seng-Pan U., Zhihua Wang, Rui Paulo Martins:
A 12-bit 110MS/s 4-stage single-opamp pipelined SAR ADC with ratio-based GEC technique. ESSCIRC 2012: 265-268 - [c14]Guohe Yin, He Gong Wei, U-Fat Chio, Sai-Weng Sin, Seng-Pan U., Zhihua Wang, Rui Paulo Martins:
A 0.024 mm2 4.9 fJ 10-bit 2 MS/s SAR ADC in 65 nm CMOS. ESSCIRC 2012: 377-380 - 2011
- [c13]Si-Seng Wong, U. Fat Chio, Chi-Hang Chan, Hou-Lon Choi, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
A 4.8-bit ENOB 5-bit 500MS/s binary-search ADC with minimized number of comparators. A-SSCC 2011: 73-76 - [c12]Chi-Hang Chan, Yan Zhu, U. Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS. A-SSCC 2011: 233-236 - [c11]U. Fat Chio, Chi-Hang Chan, Hou-Lon Choi, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins:
A 7-bit 300-MS/s subranging ADC with embedded threshold & gain-loss calibration. ESSCIRC 2011: 363-366 - [c10]He Gong Wei, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti:
A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS. ISSCC 2011: 188-190 - 2010
- [j7]Yan Zhu, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti:
A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS. IEEE J. Solid State Circuits 45(6): 1111-1121 (2010) - [j6]He Gong Wei, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins:
A Rapid Power-Switchable Track-and-Hold Amplifier in 90-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 57-II(1): 16-20 (2010) - [j5]U-Fat Chio, He Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti:
Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC. IEEE Trans. Circuits Syst. II Express Briefs 57-II(8): 607-611 (2010) - [j4]Yan Zhu, U. Fat Chio, He Gong Wei, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins:
Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs. VLSI Design 2010: 706548:1-706548:8 (2010) - [c9]Sai-Weng Sin, Li Ding, Yan Zhu, He Gong Wei, Chi-Hang Chan, U. Fat Chio, Seng-Pan U, Rui Paulo Martins, Franco Maloberti:
An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&H. ESSCIRC 2010: 218-221 - [c8]Guohe Yin, U. Fat Chio, He Gong Wei, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Zhihua Wang:
An ultra low power 9-bit 1-MS/s pipelined SAR ADC for bio-medical applications. ICECS 2010: 878-881 - [c7]Yan Zhu, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins:
A voltage feedback charge compensation technique for split DAC architecture in SAR ADCs. ISCAS 2010: 4061-4064
2000 – 2009
- 2008
- [j3]Chua-Chin Wang, Tzung-Je Lee, U. Fat Chio, Yu-Tzu Hsiao, Jia-Jin Chen:
A 570-kbps ASK demodulator without external capacitors for low-frequency wireless bio-implants. Microelectron. J. 39(1): 130-136 (2008) - [j2]Sai-Weng Sin, U-Fat Chio, Seng-Pan U., Rui Paulo Martins:
Statistical Spectra and Distortion Analysis of Time-Interleaved Sampling Bandwidth Mismatch. IEEE Trans. Circuits Syst. II Express Briefs 55-II(7): 648-652 (2008) - [c6]U. Fat Chio, He Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins:
A self-timing switch-driving register by precharge-evaluate logic for high-speed SAR ADCs. APCCAS 2008: 1164-1167 - [c5]He Gong Wei, U. Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins:
A process- and temperature- insensitive current-controlled delay generator for sampled-data systems. APCCAS 2008: 1192-1195 - [c4]Yan Zhu, U. Fat Chio, He Gong Wei, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins:
A power-efficient capacitor structure for high-speed charge recycling SAR ADCs. ICECS 2008: 642-645 - [c3]He Gong Wei, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins:
A power scalable 6-bit 1.2GS/s flash ADC with power on/off Track-and-Hold and preamplifier. ISCAS 2008: 5-8 - 2006
- [c2]Chua-Chin Wang, Chi-Chun Huang, Tzung-Je Lee, U. Fat Chio:
A Linear LDO Regulator with Modified NMCF Frequency Compensation Independent of Off-chip Capacitor and ESR. APCCAS 2006: 880-883 - 2005
- [j1]Chua-Chin Wang, Tzung-Je Lee, Yu-Tzu Hsiao, U. Fat Chio, Chi-Chun Huang, J.-J. J. Chin, Ya-Hsin Hsueh:
A multiparameter implantable microstimulator SOC. IEEE Trans. Very Large Scale Integr. Syst. 13(12): 1399-1402 (2005) - 2004
- [c1]Chua-Chin Wang, Ya-Hsin Hsueh, U. Fat Chio, Yu-Tzu Hsiao:
A C-less ASK demodulator for implantable neural interfacing chips. ISCAS (4) 2004: 57-60
Coauthor Index
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