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2000 – 2009
- 2003
[j4]Simon W. Moore
, Ross J. Anderson, Robert D. Mullins, George S. Taylor, Jacques J. A. Fournier:
Balanced self-checking asynchronous logic for smart card applications. Microprocess. Microsystems 27(9): 421-430 (2003)- [c14]Jacques J. A. Fournier, Simon W. Moore, Huiyun Li, Robert D. Mullins, George S. Taylor:
Security Evaluation of Asynchronous Circuits. CHES 2003: 137-151 - 2002
- [c13]George S. Taylor, Simon W. Moore, Robert D. Mullins, Peter Robinson:
Point to Point GALS Interconnect. ASYNC 2002: 69-75 - [c12]Simon W. Moore, Robert D. Mullins, Paul A. Cunningham, Ross J. Anderson, George S. Taylor:
Improving Smart Card Security Using Self-Timed Circuits. ASYNC 2002: 211-218 - 2000
- [c11]George S. Taylor, Simon W. Moore, Steve Wilcox, Peter Robinson:
An On-Chip Dynamically Recalibrated Delay Line for Embedded Self-Timed Systems. ASYNC 2000: 45-51 - [c10]Simon W. Moore, George S. Taylor, Paul A. Cunningham, Robert D. Mullins, Peter Robinson:
Self-Calibrating Clocks for Globally Asynchronous Locally Synchronous Systems. ICCD 2000: 73-78
1990 – 1999
- 1998
- [j3]George S. Taylor, Gerard M. Blair:
Reduced complexity two-phase micropipeline latch controller. IEEE J. Solid State Circuits 33(10): 1590-1593 (1998)
1980 – 1989
- 1989
- [j2]David D. Lee, Shing I. Kong, Mark D. Hill, George S. Taylor, David A. Hodges, Randy H. Katz, David A. Patterson:
A VLSI chip set for a multiprocessor workstation. I. An RISC microprocessor with coprocessor interface and support for symbolic processing. IEEE J. Solid State Circuits 24(6): 1688-1698 (1989) - 1987
- [c9]Bidyut Kumar Bose, Li-fan Pei, George S. Taylor, David A. Patterson:
Fast multiply and divide for a VLSI floating-point unit. IEEE Symposium on Computer Arithmetic 1987: 87-94 - 1986
- [c8]David A. Wood, Susan J. Eggers, Garth A. Gibson, Mark D. Hill, Joan M. Pendleton, Scott A. Ritchie, George S. Taylor, Randy H. Katz, David A. Patterson:
An In-Cache Address Translation Mechanism. ISCA 1986: 358-365 - [c7]George S. Taylor, Paul N. Hilfinger, James R. Larus, David A. Patterson, Benjamin G. Zorn:
Evaluation of the SPUR Lisp Architecture. ISCA 1986: 444-452 - 1985
- [j1]John K. Ousterhout, Gordon T. Hamachi, Robert N. Mayo, Walter S. Scott, George S. Taylor:
The Magic VLSI Layout System. IEEE Des. Test 2(1): 19-30 (1985) - [c6]George S. Taylor:
Radix 16 SRT dividers with overlapped quotient selection stages: A 225 nanosecond double precision divider for the S-1 Mark IIB. IEEE Symposium on Computer Arithmetic 1985: 64-71 - 1984
- [c5]John K. Ousterhout, Gordon T. Hamachi, Robert N. Mayo, Walter S. Scott, George S. Taylor:
Magic: A VLSI layout system. DAC 1984: 152-159 - [c4]George S. Taylor, John K. Ousterhout:
Magic's incremental design-rule checker. DAC 1984: 160-165 - 1983
- [c3]George S. Taylor:
Arithmetic on the ELXSI System 6400. IEEE Symposium on Computer Arithmetic 1983: 110-115 - 1981
- [c2]George S. Taylor:
Compatible hardware for division and square root. IEEE Symposium on Computer Arithmetic 1981: 127-134 - [c1]George S. Taylor, David A. Patterson:
VAX hardware for the proposed IEEE floating-point standard. IEEE Symposium on Computer Arithmetic 1981: 190-196
Coauthor Index
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