A 99-mm\(^2\) 0.7-W single-chip MPEG-2 422P@ML video, audio, and system encoder with a 64-Mb embedded DRAM for portable 422P@HL encoder system - Satoshi Kumaki; Hidehiro Takata; Yoshihide Ajioka; Tsukasa Ooishi; Kazuya Ishihara; Atsuo Hanami; Takaharu Tsuji; Tetsuya Watanabe; Chikayoshi Morishima; Tomoaki Yoshizawa; Hidenori Sato; Shin-ichi Hattori; et al. (IEEE J. Solid State Circuits, 2002)

A 99-mm\(^2\), 0.7-W, single-chip MPEG-2 422P@ML video, audio, and system encoder with a 64-Mbit embedded DRAM for portable 422P@HL encoder system - Satoshi Kumaki; Hidehiro Takata; Yoshihide Ajioka; Tsukasa Ooishi; Kazuya Ishihara; Atsuo Hanami; Takaharu Tsuji; Yusuke Kanehira; Tetsuya Watanabe; Chikayoshi Morishima; Tomoaki Yoshizawa; Hidenori Sato; et al. (Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, CICC 2001, San Diego, CA, USA, May 6-9, 2001, 2001)

MPEG-2 4: 2: 2@HL encoder chip set - Hidenori Sato; Hideo Ohira; Masahiko Kazayama; Ayako Harada; Masahiko Yoshimoto; Okikazu Tanno; Satoshi Kumaki; Kazuya Ishibara; Atsuo Hanami; Tetsuya Mutsumura (IEEE International Symposium on Circuits and Systems, ISCAS 2000, Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31 May 2000, Proceedings, 2000)

A 165-GOPS motion estimation processor with adaptive dual-array architecture for high quality video-encoding applications - Atsuo Hanami; Stefan Scotzniovsky; Kazuya Ishihara; Tetsuya Matsumura; Shin'ichi Takeuchi; Haruyuki Ohkuma; Koji Nishigaki; Hirokazu Suzuki; Masahiro Kazayama; Toyohiko Yoshida; Koji Tsuchihashi (Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, CICC 1998, Santa Clara, CA, USA, May 11-14, 1998, 1998)