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2020 – today
- 2025
[j14]Yansong zhu, Songwei Pei, Bingfeng Liu, Jun Gao:
AP-Net: Attention-fused volume and progressive aggregation for accurate stereo matching. Neurocomputing 612: 128685 (2025)- 2024
- [j13]Mingyu Yuan, Songwei Pei:
RAD-BNN: Regulating activation distribution for accurate binary neural network. Image Vis. Comput. 148: 105114 (2024) - [c14]Jinhong Hong, Songwei Pei, Shuhuai Wang:
Towards High-Accuracy Point Cloud Registration with Channel Self-attention and Angle Invariance. ICANN (2) 2024: 449-462 - [c13]Yinning Lu, Songwei Pei:
DFFNet: Dual-Channel Feature Fusion Network for End-to-End 6D Pose Estimation. IJCNN 2024: 1-8 - 2023
- [c12]Debei Hao, Songwei Pei:
PO-DARTS: Post-optimizing the Architectures Searched by Differentiable Architecture Search Algorithms. ICANN (9) 2023: 178-190 - [c11]Wenhua Liao
, Songwei Pei:
NMPose: Leveraging Normal Maps for 6D Pose Estimation. ICONIP (14) 2023: 178-190 - 2021
- [j12]Song Jin, Songwei Pei, Yu Wang, Yincheng Qi:
A parallel sparse triangular solve algorithm based on dependency elimination of the solution vector. Clust. Comput. 24(2): 1317-1330 (2021) - 2020
- [j11]Song Jin, Songwei Pei, Yu Wang:
A variation tolerant scheme for memristor crossbar based neural network designs via two-phase weight mapping and memristor programming. Future Gener. Comput. Syst. 106: 270-276 (2020) - [c10]Song Jin, Songwei Pei, Yu Wang:
On Improving Fault Tolerance of Memristor Crossbar Based Neural Network Designs by Target Sparsifying. DATE 2020: 91-96
2010 – 2019
- 2018
- [j10]Songwei Pei, Jingdong Zhang, Ruonan Wang:
A low-overhead RO PUF design for Xilinx FPGAs. IEICE Electron. Express 15(5): 20180093 (2018) - [j9]Songwei Pei, Song Jin:
An effective structure and flow for pre-bond TSV test. IEICE Electron. Express 15(12): 20180160 (2018) - 2017
- [c9]Songwei Pei, Alrashdi Ahmed Rabehb, Song Jin:
On-Chip Ring Oscillator Based Scheme for TSV Delay Measurement. ATS 2017: 11-16 - 2016
- [j8]Song Jin, Yinhe Han, Songwei Pei:
Statistical energy optimization on voltage-frequency island based MPSoCs in the presence of process variations. Microelectron. J. 54: 23-31 (2016) - [j7]Song Jin, Songwei Pei, Yinhe Han, Huawei Li:
A Cost-Effective Energy Optimization Framework of Multicore SoCs Based on Dynamically Reconfigurable Voltage-Frequency Islands. ACM Trans. Design Autom. Electr. Syst. 21(2): 27:1-27:14 (2016) - 2015
- [j6]Songwei Pei, Huawei Li, Song Jin, Jun Liu, Xiaowei Li:
An on-chip frequency programmable test clock generation and application method for small delay defect detection. Integr. 49: 87-97 (2015) - [j5]Weizhi Xu, Hui Yu, Dianjie Lu, Fenglong Song, Da Wang, Xiaochun Ye, Songwei Pei, Dongrui Fan, Hongtao Xie:
Corrigendum to "Fast and scalable lock methods for video coding on many-core architecture" [J. Visual Communication and Image Representation 25 (7) (2014) 1758-1762]. J. Vis. Commun. Image Represent. 26: 350 (2015) - [j4]Weizhi Xu, Hui Yu, Dianjie Lu, Fenglong Song, Da Wang, Xiaochun Ye, Songwei Pei, Dongrui Fan, Hongtao Xie:
Corrigendum to "Fast and scalable lock methods for video coding on many-core architecture" [J. Visual Communication and Image Representation 25(7) (2014) 1758-1762]. J. Vis. Commun. Image Represent. 27: 57 (2015) - [c8]Songwei Pei, Ye Geng, Huawei Li, Jun Liu, Song Jin:
Enhanced LCCG: A novel test clock generation scheme for faster-than-at-speed delay testing. ASP-DAC 2015: 514-519 - [c7]Songwei Pei, Jingdong Zhang, Yu Jin, Song Jin, Jun Liu, Weizhi Xu:
An Effective TSV Self-Repair Scheme for 3D-Stacked ICs. ACM Great Lakes Symposium on VLSI 2015: 21-26 - [c6]Song Jin, Songwei Pei, Yinhe Han, Huawei Li:
On optimizing system energy of multi-core SoCs based on dynamically reconfigurable voltage-frequency island. VLSI-DAT 2015: 1-4 - 2014
- [j3]Weizhi Xu, Hui Yu, Dianjie Lu, Fenglong Song, Da Wang, Xiaochun Ye, Songwei Pei, Dongrui Fan, Hongtao Xie:
Fast and scalable lock methods for video coding on many-core architecture. J. Vis. Commun. Image Represent. 25(7): 1758-1762 (2014) - [c5]Song Jin, Yinhe Han, Songwei Pei:
Variation-aware statistical energy optimization on voltage-frequency island based MPSoCs under performance yield constraints. ASP-DAC 2014: 720-725 - 2012
- [j2]Songwei Pei, Huawei Li, Xiaowei Li:
A High-Precision On-Chip Path Delay Measurement Architecture. IEEE Trans. Very Large Scale Integr. Syst. 20(9): 1565-1577 (2012) - [j1]Songwei Pei, Huawei Li, Xiaowei Li:
Flip-Flop Selection for Partial Enhanced Scan to Reduce Transition Test Data Volume. IEEE Trans. Very Large Scale Integr. Syst. 20(12): 2157-2169 (2012) - 2011
- [c4]Songwei Pei, Huawei Li, Xiaowei Li:
A unified test architecture for on-line and off-line delay fault detections. VTS 2011: 272-277 - 2010
- [c3]Songwei Pei, Huawei Li, Xiaowei Li:
An on-chip clock generation scheme for faster-than-at-speed delay testing. DATE 2010: 1353-1356
2000 – 2009
- 2009
- [c2]Songwei Pei, Huawei Li, Xiaowei Li:
A Low Overhead On-Chip Path Delay Measurement Circuit. Asian Test Symposium 2009: 145-150 - [c1]Songwei Pei, Huawei Li, Xiaowei Li:
Flip-Flop Selection for Transition Test Pattern Reduction Using Partial Enhanced Scan. PRDC 2009: 75-80
Coauthor Index
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