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Mayler G. A. Martins
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2020 – today
- 2023
- [j8]Zain Ul Abideen
, Tiago Diadami Perez
, Mayler G. A. Martins
, Samuel Pagliarini
:
A Security-Aware and LUT-Based CAD Flow for the Physical Synthesis of hASICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(10): 3157-3170 (2023) - 2022
- [i1]Zain Ul Abideen, Tiago Diadami Perez, Mayler G. A. Martins, Samuel Pagliarini:
A Security-aware and LUT-based CAD Flow for the Physical Synthesis of eASICs. CoRR abs/2207.05413 (2022) - 2020
- [j7]Mayler G. A. Martins
, Samuel N. Pagliarini
, Mehmet Meric Isgenc
, Lawrence T. Pileggi:
From Virtual Characterization to Test-Chips: DFM Analysis Through Pattern Enumeration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(2): 520-532 (2020) - [j6]Mehmet Meric Isgenc
, Mayler G. A. Martins
, V. Mohammed Zackriya
, Samuel N. Pagliarini
, Lawrence T. Pileggi
:
Logic IP for Low-Cost IC Design in Advanced CMOS Nodes. IEEE Trans. Very Large Scale Integr. Syst. 28(2): 585-595 (2020)
2010 – 2019
- 2018
- [j5]Iuri Albandes Cunha Gomes, Alejandro Serrano-Cases
, Mayler G. A. Martins, Antonio Martínez-Álvarez
, Sergio Cuenca-Asensi
, Fernanda Lima Kastensmidt:
Design of approximate-TMR using approximate library and heuristic approaches. Microelectron. Reliab. 88-90: 898-902 (2018) - [j4]Augusto Neutzling
, Mayler G. A. Martins, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas:
A Simple and Effective Heuristic Method for Threshold Logic Identification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(5): 1023-1036 (2018) - [j3]Samuel N. Pagliarini
, Mehmet Meric Isgenc, Mayler G. A. Martins
, Lawrence T. Pileggi:
Application and Product-Volume-Specific Customization of BEOL Metal Pitch. IEEE Trans. Very Large Scale Integr. Syst. 26(9): 1627-1636 (2018) - [c18]Iuri Albandes Cunha Gomes, Alejandro Serrano-Cases
, Antonio J. Sanchez-Clemente, Mayler G. A. Martins, Antonio Martínez-Álvarez
, Sergio Cuenca-Asensi
, Fernanda Lima Kastensmidt:
Improving approximate-TMR using multi-objective optimization genetic algorithm. LATS 2018: 1-6 - 2017
- [c17]Samuel Pagliarini
, Mayler G. A. Martins, Lawrence T. Pileggi:
Virtual characterization for exhaustive DFM evaluation of logic cell libraries. ISQED 2017: 93-98 - 2015
- [j2]Felipe S. Marranghello, Vinicius Callegaro, Mayler G. A. Martins, André Inácio Reis, Renato P. Ribas:
Factored Forms for Memristive Material Implication Stateful Logic. IEEE J. Emerg. Sel. Topics Circuits Syst. 5(2): 267-278 (2015) - [j1]Iuri A. C. Gomes, Mayler G. A. Martins, André Inácio Reis, Fernanda Lima Kastensmidt
:
Exploring the use of approximate TMR to mask transient faults in logic with low area overhead. Microelectron. Reliab. 55(9-10): 2072-2076 (2015) - [c16]Mayler G. A. Martins, Felipe S. Marranghello, Joseph S. Friedman, Alan V. Sahakian
, Renato P. Ribas, André Inácio Reis:
Enhanced Spin-Diode Synthesis Using Logic Sharing. DSD 2015: 218-224 - [c15]Vinicius Callegaro, Felipe S. Marranghello, Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis:
Bottom-up disjoint-support decomposition based on cofactor and boolean difference analysis. ICCD 2015: 680-687 - [c14]Felipe S. Marranghello, Vinicius Callegaro, Mayler G. A. Martins, André Inácio Reis, Renato P. Ribas:
Improved logic synthesis for memristive stateful logic using multi-memristor implication. ISCAS 2015: 181-184 - [c13]Mayler G. A. Martins, Jody Maick Matos, Renato P. Ribas, André Inácio Reis, Guilherme Schlinker, Lucio Rech, Jens Michelsen:
Open Cell Library in 15nm FreePDK Technology. ISPD 2015: 171-178 - [c12]Iuri A. C. Gomes, Mayler G. A. Martins, André Inácio Reis, Fernanda Lima Kastensmidt
:
Using only redundant modules with approximate logic to reduce drastically area overhead in TMR. LATS 2015: 1-6 - 2014
- [c11]Matheus T. Moreira, Augusto Neutzling, Mayler G. A. Martins, André Inácio Reis, Renato P. Ribas, Ney Calazans
:
Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible? ASYNC 2014: 53-60 - [c10]Augusto Neutzling, Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis:
A constructive approach for threshold logic circuit synthesis. ISCAS 2014: 385-388 - [c9]Iuri A. C. Gomes, Mayler G. A. Martins, Fernanda Lima Kastensmidt
, André Inácio Reis, Renato P. Ribas, Sylvain P. Novales:
Methodology for achieving best trade-off of area and fault masking coverage in ATMR. LATW 2014: 1-6 - 2013
- [c8]Lucas Machado, Mayler G. A. Martins, Vinicius Callegaro, Renato P. Ribas, André Inácio Reis:
Iterative remapping respecting timing constraints. ISVLSI 2013: 236-241 - [c7]Vinicius Callegaro, Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis:
Read-polarity-once Boolean functions. SBCCI 2013: 1-6 - [c6]Mayler G. A. Martins, Felipe S. Marranghello, Joseph S. Friedman, Alan V. Sahakian
, Renato P. Ribas, André Inácio Reis:
Spin diode network synthesis using functional composition. SBCCI 2013: 1-6 - [c5]Augusto Neutzling, Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis:
Synthesis of threshold logic gates to nanoelectronics. SBCCI 2013: 1-6 - 2012
- [c4]Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis:
Functional composition: A new paradigm for performing logic synthesis. ISQED 2012: 236-242 - [c3]Lucas Machado, Mayler G. A. Martins, Vinicius Callegaro, Renato P. Ribas, André Inácio Reis:
KL-cut based digital circuit remapping. NORCHIP 2012: 1-4 - 2011
- [c2]Mayler G. A. Martins, Vinicius Callegaro, Renato P. Ribas, André Inácio Reis:
Efficient method to compute minimum decision chains of Boolean functions. ACM Great Lakes Symposium on VLSI 2011: 419-422 - 2010
- [c1]Mayler G. A. Martins, Leomar S. da Rosa Jr., Anders B. Rasmussen, Renato P. Ribas, André Inácio Reis:
Boolean factoring with multi-objective goals. ICCD 2010: 229-234
Coauthor Index
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