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2020 – today
- 2022
[j7]Haocheng Li
, Wing-Kai Chow, Gengjie Chen, Bei Yu, Evangeline F. Y. Young:
Pin-Accessible Legalization for Mixed-Cell-Height Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(1): 143-154 (2022)
2010 – 2019
- 2019
- [c15]Wen-Hao Liu, Stefanus Mantik, Wing-Kai Chow, Yixiao Ding, Amin Farshidi, Gracieli Posser:
ISPD 2019 Initial Detailed Routing Contest and Benchmark with Advanced Routing Rules. ISPD 2019: 147-151 - 2018
- [j6]Gengjie Chen, Chak-Wa Pui, Wing-Kai Chow, Ka-Chun Lam, Jian Kuang, Evangeline F. Y. Young, Bei Yu:
RippleFPGA: Routability-Driven Simultaneous Packing and Placement for Modern FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(10): 2022-2035 (2018) - [c14]Haocheng Li, Wing-Kai Chow, Gengjie Chen, Evangeline F. Y. Young, Bei Yu:
Routability-driven and fence-aware legalization for mixed-cell-height circuits. DAC 2018: 150:1-150:6 - [c13]Charles J. Alpert, Wing-Kai Chow, Kwangsoo Han, Andrew B. Kahng, Zhuo Li, Derong Liu, Sriram Venkatesh:
Prim-Dijkstra Revisited: Achieving Superior Timing-driven Routing Trees. ISPD 2018: 10-17 - [c12]Stefanus Mantik, Gracieli Posser, Wing-Kai Chow, Yixiao Ding, Wen-Hao Liu:
ISPD 2018 Initial Detailed Routing Contest and Benchmarks. ISPD 2018: 140-143 - 2017
- [c11]Wing-Kai Chow, Jian Kuang, Peishan Tu, Evangeline F. Y. Young:
Fence-aware detailed-routability driven placement. SLIP 2017: 1-7 - [c10]Peishan Tu, Wing-Kai Chow, Evangeline F. Y. Young:
Timing driven routing tree construction. SLIP 2017: 1-8 - 2016
- [j5]Wing-Kai Chow, Evangeline F. Y. Young:
Placement: From Wirelength to Detailed Routability. IPSJ Trans. Syst. LSI Des. Methodol. 9: 2-12 (2016) - [j4]Jian Kuang, Wing-Kai Chow, Evangeline F. Y. Young:
Triple Patterning Lithography Aware Optimization and Detailed Placement Algorithms for Standard Cell-Based Designs. IEEE Trans. Very Large Scale Integr. Syst. 24(4): 1319-1332 (2016) - [c9]Wing-Kai Chow, Chak-Wa Pui, Evangeline F. Y. Young:
Legalization algorithm for multiple-row height standard cell design. DAC 2016: 83:1-83:6 - [c8]Chak-Wa Pui, Gengjie Chen, Wing-Kai Chow, Ka-Chun Lam, Jian Kuang, Peishan Tu, Hang Zhang, Evangeline F. Y. Young, Bei Yu:
RippleFPGA: a routability-driven placement for large-scale heterogeneous FPGAs. ICCAD 2016: 67 - 2015
- [c7]Jian Kuang, Wing-Kai Chow, Evangeline F. Y. Young:
A robust approach for process variation aware mask optimization. DATE 2015: 1591-1594 - 2014
- [j3]Wing-Kai Chow, Liang Li, Evangeline F. Y. Young, Chiu-Wing Sham:
Obstacle-avoiding rectilinear Steiner tree construction in sequential and parallel approach. Integr. 47(1): 105-114 (2014) - [c6]Jian Kuang, Wing-Kai Chow, Evangeline F. Y. Young:
Triple patterning lithography aware optimization for standard cell based design. ICCAD 2014: 108-115 - [c5]Wing-Kai Chow, Jian Kuang, Xu He, Wenzan Cai, Evangeline F. Y. Young:
Cell density-driven detailed placement with displacement constraint. ISPD 2014: 3-10 - 2013
- [c4]Xu He, Tao Huang, Wing-Kai Chow, Jian Kuang, Ka-Chun Lam, Wenzan Cai, Evangeline F. Y. Young:
Ripple 2.0: high quality routability-driven placement via global router integration. DAC 2013: 152:1-152:6 - [c3]Xu He, Wing-Kai Chow, Evangeline F. Y. Young:
SRP: simultaneous routing and placement for congestion refinement. ISPD 2013: 108-113 - 2012
- [j2]Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham:
A new clock network synthesizer for modern VLSI designs. Integr. 45(2): 121-131 (2012) - [j1]Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham:
Fast Power- and Slew-Aware Gated Clock Tree Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 20(11): 2094-2103 (2012) - 2010
- [c2]Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham, Evangeline F. Y. Young:
A dual-MST approach for clock network synthesis. ASP-DAC 2010: 467-473 - [c1]Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham:
Clock Network Synthesis with Concurrent Gate Insertion. PATMOS 2010: 228-237
Coauthor Index
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