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ORCIDParimal Patel
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2000 – 2009
- 2008
[c25]Chirag Parikh, Parimal Patel:
Selection and Implementation of an EAP Authentication Protocol for Hand-held Devices. CAINE 2008: 255-260- 2007
- [j3]Christopher J. Martinez, Wei-Ming Lin, Parimal Patel:
Optimal XOR hashing for non-uniformly distributed address lookup in computer networks. J. Netw. Comput. Appl. 30(4): 1397-1427 (2007) - [c24]Parimal Patel, Chirag Parikh:
Low Power Implementation of AES (RIJNDAEL) Algorithm. CATA 2007: 7-11 - [c23]Parimal Patel, Ashok Kumar Tummala:
Detecting TCP Port Scans Generated by NMAP using Reconfigurable Hardware. CATA 2007: 266-270 - [c22]Sunil K. Venugopal, Chirag Parikh, Parimal Patel:
Implementation of an IEEE 802.11i based Wireless Security System. HPCNCS 2007: 136-143 - [c21]Ashok Kumar Tummala, Parimal Patel:
Distributed IDS using Reconfigurable Hardware. IPDPS 2007: 1-6 - [c20]Parimal Patel:
Tutorial IND2A: Embedded Systems Design with Xilinx Virtex-5 Series FPGA. VLSI Design 2007: 16 - 2006
- [c19]Devang Pandya, Christopher J. Martinez, Wei-Ming Lin, Parimal Patel:
Advanced hashing techniques for non-uniformly distributed IP address lookup. Communications and Computer Networks 2006: 46-51 - [c18]Devang Pandya, Christopher J. Martinez, Wei-Ming Lin, Parimal Patel:
The Design of Efficient Hashing Techniques for IP Address Lookup. LCN 2006: 531-532 - [c17]Parimal Patel:
Embedded Systems Design Using FPGA. VLSI Design 2006: 20 - 2005
- [j2]Parimal Patel, Chirag Parikh:
IDEA cryptographic processor in FPGA. J. Comput. Methods Sci. Eng. 5(4): 201-208 (2005) - [c16]Christopher J. Martinez, Wei-Ming Lin, Parimal Patel:
Optimal XOR hashing for a linearly distributed address lookup in computer networks. ANCS 2005: 203-210 - [c15]Bala Krishnan D. Achie, Ajaykrishna Sreehari, Parimal Patel:
FPGA Based Implementation of MD5 Message-Digest Algorithm for IPSEC Authentication. CAINE 2005: 372-375 - [c14]Parimal Patel, Ashok Kumar Tummala, Hari Babu Ramineni, Wei-Ming Lin:
Improved Design and Implementation of Network Intrusion Detection System for Gigabit Network Traffic Using FPGA. CAINE 2005: 382-386 - 2004
- [c13]Chirag Parikh, Parimal Patel:
Design and Implementation of AES (Rijndael) Algorithm. CAINE 2004: 85-89 - [c12]Sumit N. Vora, Parimal Patel:
Architecture for Context-driven Packet Payload Processing Engine. CAINE 2004: 115-119 - [c11]Apurva Mistry, Parimal Patel:
Prototyped Embedded Application for IGMP Version 2 Protocol. CAINE 2004: 138-142 - [c10]Narayanam Ranganadh, Parimal Patel, Artyom M. Grigoryan:
Implementation of the DFT Using Radix-2 and Paired Transform Algorithms. CAINE 2004: 148-153 - [c9]Wei-Ming Lin, Ramu Madhavaram, Parimal Patel, Fred Hudson:
A Real-Time Ad Hoc Packet Matching Technique for Hardware-Based Network Intrusion Detection Systems. CATA 2004: 382- - [e1]Parimal Patel:
17th International Conference on Computer Applications in Industry and Engineering, CAINE 2004, November 17-19, 2004, Florida Mall Hotel, Orlando, Florida, USA. ISCA 2004, ISBN 1-880843-53-6 [contents] - 2003
- [c8]Parimal Patel, Chirag Parikh:
Design and Implementation of AES (Rijndael) Algorithm. CAINE 2003: 126-130 - [c7]Parimal Patel, Chirag Parikh:
An Efficient Design and Implementation of DES and Triple-DES Algorithms. CATA 2003: 40-43 - [c6]Parimal Patel, Venkataramana Reddipalli:
Design Considerations of Implementing a Superscalar CPU in FPGA. CATA 2003: 296-299 - 2002
- [c5]Venkataramana Reddipalli, Sri Pallavi Padala, Parimal Patel:
Design and Implementation of ATM NIC in FPGA. CAINE 2002: 193-196 - 2001
- [c4]Parimal Patel, Harish Maiya:
Implementation comparison of multicasting policies in an ATM switch. CATA 2001: 505-510 - [c3]Parimal Patel, Venkataramana Reddipalli:
Implementation of write relocatable coherency protocol in multiple processor architectures. CATA 2001: 511-516
1990 – 1999
- 1999
- [c2]Parimal Patel, Chung Chang:
Performance improvement using fill unit. CATA 1999: 254-259 - 1998
- [c1]Parimal Patel, Saad Zahid:
Design Considerations in an ATM Switch Design. ICCCN 1998: 92-98 - 1992
- [j1]Parimal Patel, Hemal N. Kothari, James F. Robb:
Development of an ASIC set for signal processing. IEEE Micro 12(6): 24-33 (1992)
Coauthor Index
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