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1990 – 1999
- 1997
[j4]Hideo Kato, Masataka Matsui, Katsuhiko Sato, H. Shibata, K. Hashimoto, Takayuki Ootani, Kiyofumi Ochii:
SRAM cell stability under the influence of parasitic resistances and data holding voltage as a stability prober. IEEE J. Solid State Circuits 32(2): 232-237 (1997)- 1992
- [j3]Hideo Kato, Katsuhiko Sato, Masataka Matsui, H. Shibata, K. Hashimoto, Takayuki Ootani, Kiyofumi Ochii:
Consideration of poly-Si loaded cell capacity limits for low-power and high-speed SRAMs. IEEE J. Solid State Circuits 27(4): 683-685 (1992) - 1990
- [j2]Takayuki Ootani, Shigeyuki Hayakawa, Masakazu Kakumu, Akira Aona, Masaaki Kinugawa, Hideki Takeuchi, Kazuhiro Noguchi, Tomoaki Yabe, Katsuhiko Sato, Kenji Maeguchi, Kiyofumi Ochii:
A 4-Mb CMOS SRAM with a PMOS thin-film-transistor load cell. IEEE J. Solid State Circuits 25(5): 1082-1092 (1990)
1980 – 1989
- 1989
- [j1]Masataka Matsui, Hiroshi Momose, Yukihiro Urakawa, Takeo Maeda, Azuma Suzuki, Nobuaki Urakawa, Katsuhiko Sato, Jun'ichi Matsunaga, Kiyofumi Ochii:
An 8-ns 1-Mbit ECL BiCMOS SRAM with double-latch ECL-to-CMOS-level converters. IEEE J. Solid State Circuits 24(5): 1226-1232 (1989)
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