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ORCIDKatsumi Homma
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2020 – today
- 2022
[c9]Natsuki Morita, Hayato Dan, Katsumi Homma, Hitoshi Yanami, Shota Suginouchi, Mizuho Sato, Hajime Mizuyama, Masatoshi Ogawa:
Equilibrium Search Technique Using Genetic Algorithm and Replicator Dynamics and Its Application to Food Supply Chain Model. KES-IDT 2022: 363-374
2010 – 2019
- 2018
- [c8]Yoshinobu Iimura, Masashi Wakaiki, Katsumi Homma, Yuhei Umeda, Junji Kaneko, Hiroyuki Higuchi, Kazumi Kubota, Naoya Asami, Kazuto Ikeda:
Simultaneous Optimization of Statistical Model and Control Input Plan. ACC 2018: 1072-1077 - 2015
- [c7]Naoki Hamada, Katsumi Homma, Hiroyuki Higuchi, Hideyuki Kikuchi:
Population Synthesis via k-Nearest Neighbor Crossover Kernel. ICDM 2015: 763-768 - [i1]Naoki Hamada, Katsumi Homma, Hiroyuki Higuchi, Hideyuki Kikuchi:
Population Synthesis via k-Nearest Neighbor Crossover Kernel. CoRR abs/1508.06483 (2015) - 2013
- [c6]Shintaro Tsuji, Akihisa Fukuda, Ayako Yagahara, Katsumi Homma, Naoki Nishimoto, Masahito Uesugi, Katsuhiko Ogasawara
:
An Ontology Design for Visualizing Implicit Knowledge of the Radiotherapy Risk. MedInfo 2013: 994 - 2012
- [c5]Tsutomu Ishida, Izumi Nitta, Katsumi Homma, Yuzi Kanazawa, Hiroaki Komatsu:
Speed-path analysis for multi-path failed latches with random variation. ISQED 2012: 545-552 - 2010
- [c4]Yu Liu, Masato Yoshioka, Katsumi Homma, Toshiyuki Shibuya, Yuzi Kanazawa:
Generation of yield-embedded Pareto-front for simultaneous optimization of yield and performances. DAC 2010: 909-912
2000 – 2009
- 2009
- [j1]Yu Liu, Masato Yoshioka, Katsumi Homma, Toshiyuki Shibuya:
Find the 'Best' Solution from Multiple Analog Topologies via Pareto-Optimality. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3035-3043 (2009) - [c3]Yu Liu, Masato Yoshioka, Katsumi Homma, Toshiyuki Shibuya:
Efficiently finding the 'best' solution with multi-objectives from multiple topologies in topology library of analog circuit. ASP-DAC 2009: 498-503 - 2008
- [c2]Katsumi Homma, Izumi Nitta, Toshiyuki Shibuya:
Non-Gaussian Statistical Timing models of die-to-die and within-die parameter variations for full chip analysis. ASP-DAC 2008: 292-297
1990 – 1999
- 1998
- [c1]Hisakazu Edamatsu, Katsumi Homma, Masaru Kakimoto, Yutaka Koike, Kinya Tabuchi:
Pre-layout Delay Calculation Specification for CMOS ASIC Libraries. ASP-DAC 1998: 241-248
Coauthor Index
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