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ORCIDJoseph J. Sharkey
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2000 – 2009
- 2008
[j5]Joseph J. Sharkey, Jason Loew, Dmitry V. Ponomarev:
Reducing register pressure in SMT processors through L2-miss-driven early register release. ACM Trans. Archit. Code Optim. 5(3): 13:1-13:28 (2008)- [j4]Deniz Balkan, Joseph J. Sharkey, Dmitry V. Ponomarev, Kanad Ghose:
Predicting and Exploiting Transient Values for Reducing Register File Pressure and Energy Consumption. IEEE Trans. Computers 57(1): 82-95 (2008) - [j3]Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose:
Selective Writeback: Reducing Register File Pressure and Energy Consumption. IEEE Trans. Very Large Scale Integr. Syst. 16(6): 650-661 (2008) - [c15]Robert J. LaDuca, Joseph J. Sharkey, Dmitry V. Ponomarev:
Hiding Communication Delays in Clustered Microarchitectures. SBAC-PAD 2008: 107-114 - 2007
- [j2]Joseph J. Sharkey, Dmitry V. Ponomarev:
Exploiting Operand Availability for Efficient Simultaneous Multithreading. IEEE Trans. Computers 56(2): 208-223 (2007) - [c14]Joseph J. Sharkey, Dmitry V. Ponomarev:
An L2-miss-driven early register deallocation for SMT processors. ICS 2007: 138-147 - [c13]Joseph J. Sharkey, Alper Buyuktosunoglu, Pradip Bose:
Evaluating design tradeoffs in on-chip power management for CMPs. ISLPED 2007: 44-49 - 2006
- [j1]Joseph J. Sharkey, Dmitry V. Ponomarev, Kanad Ghose, Oguz Ergin
:
Instruction packing: Toward fast and energy-efficient instruction scheduling. ACM Trans. Archit. Code Optim. 3(2): 156-181 (2006) - [c12]Joseph J. Sharkey, Deniz Balkan, Dmitry Ponomarev:
Adaptive reorder buffers for SMT processors. PACT 2006: 244-253 - [c11]Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose:
SPARTAN: speculative avoidance of register allocations to transient values for performance and energy efficiency. PACT 2006: 265-274 - [c10]Joseph J. Sharkey, Nayef Abu-Ghazeleh, Dmitry V. Ponomarev, Kanad Ghose, Aneesh Aggarwal:
Trade-Offs in Transient Fault Recovery Schemes for Redundant Multithreaded Processors. HiPC 2006: 135-147 - [c9]Joseph J. Sharkey, Dmitry V. Ponomarev:
Efficient instruction schedulers for SMT processors. HPCA 2006: 288-298 - [c8]Joseph J. Sharkey, Dmitry Ponomarev:
Balancing ILP and TLP in SMT Architectures through Out-of-Order Instruction Dispatch. ICPP 2006: 329-336 - [c7]Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev, Aneesh Aggarwal:
Address-Value Decoupling for Early Register Deallocation. ICPP 2006: 337-346 - [c6]Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose:
Selective writeback: exploiting transient values for energy-efficiency and performance. ISLPED 2006: 37-42 - 2005
- [c5]Joseph J. Sharkey, Dmitry V. Ponomarev:
Non-uniform Instruction Scheduling. Euro-Par 2005: 540-549 - [c4]Joseph J. Sharkey, Dmitry V. Ponomarev:
Instruction Recirculation: Eliminating Counting Logic in Wakeup-Free Schedulers. Euro-Par 2005: 550-559 - [c3]Joseph J. Sharkey, Kanad Ghose, Dmitry V. Ponomarev, Oguz Ergin:
Power-Efficient Wakeup Tag Broadcast. ICCD 2005: 654-661 - [c2]Joseph J. Sharkey, Dmitry V. Ponomarev, Kanad Ghose, Oguz Ergin:
Instruction packing: reducing power and delay of the dynamic scheduling logic. ISLPED 2005: 30-35 - 2004
- [c1]Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose, Oguz Ergin:
Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization. PACS 2004: 15-29
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