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Nam-Seog Kim
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2020 – today
- 2024
- [j11]Jin-Woo Kim, Jun-Seok Beom, Hong-Sub Lee, Nam-Seog Kim:
A Compact Model for Interface-Type Self-Rectifying Resistive Memory With Experiment Verification. IEEE Access 12: 5081-5091 (2024) - [j10]Nam-Seog Kim:
A 2.4 GHz Wide-Range CMOS Current-Mode Class-D PA with HD2 Suppression for Internet of Things Applications. Sensors 24(5): 1616 (2024) - 2022
- [j9]Nam-Seog Kim:
A 10-Bit, 600 MS/s Multi-Mode Direct-Sampling DAC-Based Transmitter. IEEE Access 10: 125696-125706 (2022) - 2021
- [j8]Jaewon Choi, Nam-Seog Kim:
A Spurious and Oscillator Pulling Free CMOS Quadrature LO-Generator for Cellular NB-IoT. IEEE Trans. Very Large Scale Integr. Syst. 29(12): 2098-2109 (2021)
2010 – 2019
- 2018
- [j7]Nam-Seog Kim, Jan M. Rabaey:
A Dual-Resolution Wavelet-Based Energy Detection Spectrum Sensing for UWB-Based Cognitive Radios. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(7): 2279-2292 (2018) - [c10]Jaewon Choi, Nam-Seog Kim, Juyoung Han, Thomas Byunghak Cho:
A 0.46-2.1 GHz Spurious and Oscillator-Pulling Free LO Generator for Cellular NB-IoT Transmitter with 23 dBm Integrated PAs in 28nm CMOS. A-SSCC 2018: 299-302 - 2017
- [j6]Chih-Wei Yao, Ronghua Ni, Chung Lau, Wanghua Wu, Kunal Godbole, Yongrong Zuo, Sangsoo Ko, Nam-Seog Kim, Sangwook Han, Ikkyun Jo, Joonhee Lee, Juyoung Han, Daehyeon Kwon, Chulho Kim, Shinwoong Kim, Sang Won Son, Thomas Byunghak Cho:
A 14-nm 0.14-psrms Fractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration. IEEE J. Solid State Circuits 52(12): 3446-3457 (2017) - [c9]Chih-Wei Yao, Wing Fai Loke, Ronghua Ni, Yongping Han, Haoyang Li, Kunal Godbole, Yongrong Zuo, Sangsoo Ko, Nam-Seog Kim, Sangwook Han, Ikkyun Jo, Joonhee Lee, Juyoung Han, Daehyeon Kwon, Chulho Kim, Shinwoong Kim, Sang Won Son, Thomas Byunghak Cho:
24.8 A 14nm fractional-N digital PLL with 0.14psrms jitter and -78dBc fractional spur for cellular RFICs. ISSCC 2017: 422-423 - 2016
- [j5]Nam-Seog Kim, Byungkyu Park, Kang-Dae Lee:
A knowledge based freight management decision support system incorporating economies of scale: multimodal minimum cost flow optimization approach. Inf. Technol. Manag. 17(1): 81-94 (2016) - [j4]Nam-Seog Kim, Jan M. Rabaey:
A High Data-Rate Energy-Efficient Triple-Channel UWB-Based Cognitive Radio. IEEE J. Solid State Circuits 51(4): 809-820 (2016) - 2015
- [c8]Nam-Seog Kim, Jan M. Rabaey:
A 3.1-10.6GHz wavelet-based dual-resolution spectrum sensing with harmonic rejection mixers. ESSCIRC 2015: 303-306 - [c7]Nam-Seog Kim, Jan M. Rabaey:
A 1Gb/s energy efficient triple-channel UWB-based cognitive radio. VLSIC 2015: 96- - 2014
- [b1]Nam-Seog Kim:
An Energy-Efficient Triple-Channel UWB-based Cognitive Radio. University of California, Berkeley, USA, 2014 - 2010
- [j3]Uksong Kang, Hoeju Chung, Seongmoo Heo, Dukha Park, Hoon Lee, Jin Ho Kim, Soon-Hong Ahn, Sooho Cha, Jaesung Ahn, Dukmin Kwon, Jaewook Lee, Han-Sung Joo, Woo-Seop Kim, Dong Hyeon Jang, Nam-Seog Kim, Jung-Hwan Choi, Tae-Gyeong Chung, Jei-Hwan Yoo, Joo-Sun Choi, Changhyun Kim, Young-Hyun Jun:
8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology. IEEE J. Solid State Circuits 45(1): 111-119 (2010)
2000 – 2009
- 2009
- [c6]Uksong Kang, Hoeju Chung, Seongmoo Heo, Soon-Hong Ahn, Hoon Lee, Sooho Cha, Jaesung Ahn, Dukmin Kwon, Jin Ho Kim, Jaewook Lee, Han-Sung Joo, Woo-Seop Kim, Hyun-Kyung Kim, Eun-Mi Lee, So-Ra Kim, Keum-Hee Ma, Dong-Hyun Jang, Nam-Seog Kim, Man-Sik Choi, Sae-Jang Oh, Jung-Bae Lee, Tae-Kyung Jung, Jei-Hwan Yoo, Changhyun Kim:
8Gb 3D DDR3 DRAM using through-silicon-via technology. ISSCC 2009: 130-131 - 2008
- [c5]Stanley Yuan-Shih Chen, Nam-Seog Kim, Jan M. Rabaey:
Multi-mode sub-Nyquist rate digital-to-analog conversion for direct waveform synthesis. SiPS 2008: 112-117 - 2005
- [c4]Nam-Seog Kim, Uk-Rae Cho, Hyun-Geun Byun:
Low voltage wide range DLL-based quad-phase core clock generator for high speed network SRAM application. CICC 2005: 533-536 - [c3]Nam-Seog Kim, Uk-Rae Cho, Hyun-Geun Byun:
A pseudo-differential CMOS receiver insensitive to input common mode level. ISCAS (1) 2005: 440-443 - 2004
- [j2]Yong-Jin Yoon, Hyuck In Kwon, Jong Duk Lee, Byung Gook Park, Nam-Seog Kim, Uk-Rae Cho, Hyun-Geun Byun:
Synchronous mirror delay for multiphase locking. IEEE J. Solid State Circuits 39(1): 150-156 (2004) - 2003
- [j1]Uk-Rae Cho, Tae-Hyoung Kim, Yong-Jin Yoon, Jong-Cheol Lee, Dae-Gi Bae, Nam-Seog Kim, Kang-Young Kim, Young-Jae Son, Jeong-Suk Yang, Kwon-Il Sohn, Sung-Tae Kim, In-Yeol Lee, Kwang-Jin Lee, Tae-Gyoung Kang, Su-Chul Kim, Kee-Sik Ahn, Hyun-Geun Byun:
A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM. IEEE J. Solid State Circuits 38(11): 1943-1951 (2003) - [c2]Nam-Seog Kim, Yong-Jin Yoon, Uk-Rae Cho, Hyun-Geun Byun:
Programmable and automatically adjustable on-die terminator for DDR3-SRAM interface. CICC 2003: 391-394 - [c1]Nam-Seog Kim, Yong-Jin Yoon, Uk-Rae Cho, Hyun-Geun Byun:
New dynamic logic-level converters for high performance application. ISCAS (5) 2003: 93-96
Coauthor Index
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last updated on 2024-05-08 20:56 CEST by the dblp team
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