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Radhakrishnan Sithanandam
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2020 – today
- 2020
- [c4]Sukjin Kim, Radhakrishnan Sithanandam, Woojin Seo, Mijin Lee, Sangyoung Cho, Juho Park, Hyukhoon Kwon, Namho Kim, Chanhee Jeon:
Technology Scaling of ESD Devices in State of the Art FinFET Technologies. CICC 2020: 1-6
2010 – 2019
- 2015
- [c3]N. K. Kranthi, Radhakrishnan Sithanandam, Rama Komaragiri:
Recessed MOSFET in 28 nm FDSOI for Better Breakdown Characteristics. VLSID 2015: 282-285 - 2014
- [c2]Parmanand Singh, Vivek Asthana, Radhakrishnan Sithanandam, Anand Bulusu, Sudeb Dasgupta:
Analytical Modeling of Sub-onset Current of Tunnel Field Effect Transistor. VLSID 2014: 411-414 - 2010
- [c1]Radhakrishnan Sithanandam, Mamidala Jagadesh Kumar:
A New Hetero-material Stepped Gate (HSG) SOI LDMOS for RF Power Amplifier Applications. VLSI Design 2010: 230-234
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last updated on 2024-04-25 05:48 CEST by the dblp team
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