A highly efficient full-system virtual prototype based on virtualization-assisted approach. - Wu, Hsin-I; Chen, Chi-Kang; Lu, Tsung-Ying; Tsay, Ren-Song (2018)

23.9 An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cache. - Ting, Tah-Kang Joseph; Wang, Gyh-Bin; Wang, Ming-Hung; Wu, Chun-Peng; Wang, Chun-Kai; Lo, Chun-Wei; Tien, Li-Chin; Yuan, Der-Min; Hsieh, Yung-Ching; Lai, Jenn-Shiang; Hsu, Wen-Pin; Huang, Chien-Chih; et al. (2017)

An accurate and flexible early memory system power evaluation approach using a microcomponent method. - Chen, Chi-Kang; Wu, Hsin-I; Hsiao, Chi-Ting; Tsay, Ren-Song (2016)

Poster Paper: An Accurate Crowdsourcing-Based Adaptive Fall Detection Approach Using Smart Devices. - Chen, Hsuan-Man; Chen, Chi-Kang; Wu, Hsin-I; Tsay, Ren-Song (2016)

An Accurate Crowdsourcing-Based Adaptive Fall Detection Approach Using Smart Devices. - Chen, Hsuan-Man; Chen, Chi-Kang; Wu, Hsin-I; Tsay, Ren-Song (2016)

AROMA: A highly accurate microcomponent-based approach for embedded processor power analysis. - Huang, Zih-Ci; Chen, Chi-Kang; Tsay, Ren-Song (2015)

A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs. - Luo, Pei-Wen; Chen, Chi-Kang; Sung, Yu-Hui; Wu, Wei; Shih, Hsiu-Chuan; Lee, Chia-Hsin; Lee, Kuo-Hua; Li, Ming-Wei; Lung, Mei-Chiang; Lu, Chun-Nan; Chou, Yung-Fa; Shih, Po-Lin; et al. (2015)

A basic-block power annotation approach for fast and accurate embedded software power estimation. - Lee, Chien-Min; Chen, Chi-Kang; Tsay, Ren-Song (2013)

On the interval completion of chordal graphs. - Peng, Sheng-Lung; Chen, Chi-Kang (Discret. Appl. Math., 2006)