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ORCIDKazuhito Ito
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2020 – today
- 2022
[j25]Yuki Imai, Shinichi Nishizawa
, Kazuhito Ito:
Reduction of LSI Maximum Power Consumption with Standard Cell Library of Stack Structured Cells. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 105-A(3): 487-496 (2022)- [j24]Yuya Kitazawa, Kazuhito Ito:
Register Minimization and its Application in Schedule Exploration for Area Minimization for Double Modular Redundancy LSI Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 105-A(3): 530-539 (2022) - 2020
- [j23]Kazuhito Ito:
Energy Minimization of Double Modular Redundant Conditional Processing by Common Condition Dependency. IEICE Trans. Electron. 103-C(4): 181-185 (2020)
2010 – 2019
- 2019
- [j22]Kota Chubachi, Shinichi Nishizawa, Kazuhito Ito:
Analog circuit design methodology utilizing a structure of thin BOX FDSOI. IEICE Electron. Express 16(5): 20181136 (2019) - 2018
- [j21]Kazuhito Ito, Yuto Ishihara, Shinichi Nishizawa:
Minimization of Vote Operations for Soft Error Detection in DMR Design with Error Correction by Operation Re-Execution. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(12): 2271-2279 (2018) - [c9]Seiji Nakagawa, Kazuhito Ito:
Mechanisms of Bone-conducted Ultrasonic Perception Assessed by Measurements of Acoustic Fields in the Outer Ear Canal and Vibrations of the Tympanic Membrane. EMBC 2018: 5962-5965 - 2017
- [j20]Shunsuke Tamura, Miduki Mori, Kazuhito Ito, Nobuyuki Hirose, Shuji Mori:
Study on interactions between voicing production and perception using auditory feedback paradigm. Proc. Meet. Acoust. 31(1) (2017) - 2016
- [j19]Kazuhito Ito:
Low Complexity Reed-Solomon Decoder Design with Pipelined Recursive Euclidean Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(12): 2453-2462 (2016) - [j18]Kazuhito Ito, Hiroki Hayashi:
Hardware-Efficient Local Extrema Detection for Scale-Space Extrema Detection in SIFT Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(12): 2507-2510 (2016) - [c8]Seiji Nakagawa, Takuya Hotehama, Kazuhito Ito, Tomohiro Inagaki:
Development of bone-conduction mobile phones: Assessment of hearing mechanisms by measuring psychological characteristics and acoustical properties in the outer ear canal. EMBC 2016: 5427-5430 - 2015
- [j17]Kazuhito Ito:
A Low Power and Hardware Efficient Syndrome Key Equation Solver Architecture and Its Folding with Pipelining. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(5): 1058-1066 (2015) - 2014
- [j16]Kazuhito Ito:
Energy Minimization of Full TMR Design with Optimized Selection of Temporal/Spatial TMR Mode and Supply Voltage. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(12): 2530-2539 (2014) - 2013
- [j15]Kazuhito Ito:
An Area-Time Efficient Key Equation Solver with Euclidean Algorithm for Reed-Solomon Decoders. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(2): 609-617 (2013) - [j14]Kazuhito Ito, Takuya Numata:
Valid Digit and Overflow Information to Reduce Energy Dissipation of Functional Units in General Purpose Processors. IEICE Trans. Electron. 96-C(4): 463-472 (2013) - [j13]Kazuhito Ito, Ryoto Shirasaka:
Hardware Efficient and Low Latency Implementations of Look-Ahead ACS Computation for Viterbi Decoders. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12): 2680-2688 (2013) - [j12]Kazuhito Ito, Kazuhiko Kameda:
A Method to Reduce Energy Consumption of Conditional Operations with Execution Probabilities. Inf. Media Technol. 8(2): 295-305 (2013) - [j11]Kazuhito Ito, Kazuhiko Kameda:
A Method to Reduce Energy Consumption of Conditional Operations with Execution Probabilities. IPSJ Trans. Syst. LSI Des. Methodol. 6: 60-70 (2013) - 2012
- [j10]Kazuhito Ito:
A Trace-Back Method with Source States for Viterbi Decoding of Rate-1/n Convolutional Codes. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(4): 767-775 (2012) - [j9]Kazuhito Ito, Keisuke Nasu:
A Processor Accelerator for Software Decoding of Reed-Solomon Codes. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(5): 884-893 (2012) - 2010
- [j8]Kazuhito Ito:
A Processor Accelerator for Software Decoding of BCH Codes. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(7): 1329-1337 (2010) - [j7]Hidekazu Seto, Kazuhito Ito:
A Resource Binding Method to Reduce Data Communication Power Dissipation on LSI. IPSJ Trans. Syst. LSI Des. Methodol. 3: 257-267 (2010)
2000 – 2009
- 2009
- [j6]Kazuhito Ito, Hidekazu Seto:
Reducing Power Dissipation of Data Communications on LSI with Scheduling Exploration. Inf. Media Technol. 4(2): 200-210 (2009) - [j5]Kazuhito Ito, Hidekazu Seto:
Reducing Power Dissipation of Data Communications on LSI with Scheduling Exploration. IPSJ Trans. Syst. LSI Des. Methodol. 2: 53-63 (2009) - 2005
- [c7]Masayuki Masuda, Kazuhito Ito:
Rapid and precise instruction set evaluation for application specific processor design. ISCAS (6) 2005: 6210-6213 - 2002
- [j4]Trio Adiono, Tsuyoshi Isshiki, Chawalit Honsawek, Kazuhito Ito, Dongju Li, Hiroaki Kunieda:
New Rate Control Method with Minimum Skipped Frames for Very Low Delay in H.263+ Codec. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(6): 1396-1407 (2002) - [c6]Kazuhito Ito, Daisuke Suzuki:
A high-level synthesis method for simultaneous placement and scheduling considering data communication delay. APCCAS (1) 2002: 149-154 - 2001
- [c5]Tsuyoshi Isshiki, Chawalit Honsawek, Trio Adiono, Kazuhito Ito, Tomohiko Ohtsuka, Dongju Li, Hiroaki Kunieda:
H.263+ Video Encoder/Decoder LSI Featuring System-MSPA Architecture and Improved Rate Control Method. ISAS-SCI (1) 2001: 195-200 - 2000
- [c4]Kazuhito Ito:
A scheduling and allocation method to reduce data transfer time by dynamic reconfiguration. ASP-DAC 2000: 323-328
1990 – 1999
- 1998
- [j3]Kazuhito Ito, Lori E. Lucke, Keshab K. Parhi:
ILP-based cost-optimal DSP synthesis with module selection and data format conversion. IEEE Trans. Very Large Scale Integr. Syst. 6(4): 582-594 (1998) - 1997
- [j2]Kazuhito Ito, Keshab K. Parhi:
A Generalized Technique for Register Counting and its Application to Cost-Optimal DSP Architecture Synthesis. J. VLSI Signal Process. 16(1): 57-72 (1997) - [c3]Kazuhito Ito, Takenobu Shimizugashira, Hiroaki Kunieda:
High speed bit-serial parallel processing on array architecture. ASP-DAC 1997: 667-668 - 1995
- [j1]Kazuhito Ito, Keshab K. Parhi:
Determining the minimum iteration period of an algorithm. J. VLSI Signal Process. 11(3): 229-244 (1995) - [c2]Hiroaki Kunieda, Yusong Liao, Dongju Li, Kazuhito Ito:
Automatic design for bit-serial MSPA architecture. ASP-DAC 1995 - 1994
- [c1]Kazuhito Ito, Lori E. Lucke, Keshab K. Parhi:
Module selection and data format conversion for cost-optimal DSP synthesis. ICCAD 1994: 322-329
Coauthor Index
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