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ORCIDKwang Sub Yoon
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2010 – 2019
- 2017
[c14]Jeong H. Choi, Kwang Sub Yoon:
A CMOS third order ΔΣ modulator with inverter-based integrators. SoCC 2017: 143-148- 2016
- [c13]Sang Heon Lee, Seong Jae Hyeon, Kim Jong Gu, Kwang Sub Yoon:
A CMOS 10-bit SAR ADC with threshold configuring comparator for 5 MSBs. ISOCC 2016: 255-256 - [c12]Tae-Heon Lee, Jong-Gu Kim, Kwang Sub Yoon:
A CMOS buck converter with PFM / hysteretic mode. ISOCC 2016: 347-348 - [c11]Seong Jae Hyeon, Kwang Sub Yoon, Soo Hun Yang:
A low power fourth order ΣΔ CMOS modulator with subthreshold amplifier. SoCC 2016: 275-279 - 2015
- [c10]Tae-Jin Chung, Kwang Sub Yoon:
A CMOS hysteretic DC-DC buck converter with a low output ripple voltage. ISQED 2015: 86-89 - 2014
- [c9]Gi-Yoon Lee, Kwang Sub Yoon:
Design of a low power CMOS 10bit flash-SAR ADC. SoCC 2014: 88-91 - 2013
- [c8]Kwang Sub Yoon, Keon Lee:
A CMOS high dimming ratio power-LED driver with a preloading inductor current method. ISQED 2013: 709-713 - 2012
- [c7]Keon Lee, Dong-hun Lee, Su-hun Yang, Ji-hyun Park, Kwang Sub Yoon:
Design of high dimming ratio power-LED driver with preloading inductor current methodology. ISOCC 2012: 9-12 - 2011
- [c6]Jinwoo Kim, Shin-Il Lim, Kwang Sub Yoon, Sangmin Lee:
Design of a 12-b asynchronous SAR CMOS ADC. ISOCC 2011: 70-72
2000 – 2009
- 2004
- [c5]Soo Jin Park, Byoung Hee Yoon, Kwang Sub Yoon, Heung Soo Kim:
Design of Quaternary Logic Gate Using Double Pass-Transistor Logic with Neuron MOS Down Literal Circuit. ISMVL 2004: 198-203 - 2003
- [c4]Yun Cheol Han, Kwang Il Kim, Jun Kim, Kwang Sub Yoon:
A dual band CMOS VCO with a balanced duty cycle buffer. ACM Great Lakes Symposium on VLSI 2003: 277-280
1990 – 1999
- 1999
- [c3]Hyuk-Jun Sung, Kwang Sub Yoon:
A 3.3 V high speed CMOS PLL with 3-250 MHz input locking range. ISCAS (2) 1999: 553-556 - 1996
- [c2]Jai-Sop Hyun, Kwang Sub Yoon:
A 3V-50MHz Analog CMOS Current-Mode High Frequency Filter with a Negative Resistance Load. Great Lakes Symposium on VLSI 1996: 260- - 1995
- [c1]Jong Kug Seon, Kwang Sub Yoon:
A Precision Output Conductance Model for Analog CMOS Circuit Simulations. ISCAS 1995: 1584-1587
Coauthor Index
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