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Sharvil Patil
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2020 – today
- 2024
- [j8]Rishabh Mittal
, Hajime Shibata
, Sharvil Patil
, Erik Krommenhoek, Prawal Shrestha, Gabriele Manganaro
, Anantha P. Chandrakasan
, Hae-Seung Lee
:
A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC With Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET. IEEE J. Solid State Circuits 59(4): 1158-1170 (2024) - [c9]Sharvil Patil, Asha Ganesan, Hajime Shibata, Victor Kozlov, Gerry Taylor, Qingnan Yu, Zhao Li, Zeynep Lulec, Konstantinos Vasilakopoulos, Prawal Shrestha, Donald Paterson, Raviteja Theertham, Aseer Chowdhury:
22.2 A 700MHZ-BW -164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving 3 using Digital Cancellation of DAC Errors. ISSCC 2024: 390-392 - 2023
- [c8]Sharvil Patil, Raviteja Theertham, Hajime Shibata, Victor Kozlov, Asha Ganesan, Efram Burlingame, Zhao Li, Rama Thakar, Qianqian Zhang, Yue Yin, Aathreya S. Bhat
:
A 1-MHz-Bandwidth Continuous-Time Delta-Sigma ADC Achieving >90dB SFDR and >80dB Antialiasing Using Reference-Switched Resistive Feedback DACs. CICC 2023: 1-2 - [c7]Rishabh Mittal
, Hajime Shibata, Sharvil Patil, Erik Krommenhoek, Prawal Shrestha, Gabriele Manganaro, Anantha P. Chandrakasan, Hae-Seung Lee:
A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC with Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j7]Mohammed Wagih Ismail
, Hajime Shibata
, Zhao Li
, Sharvil Patil
, Tony Chan Carusone
:
A Design Methodology for Achieving Near Nyquist Continuous Time Pipelined ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. 69(12): 4731-4740 (2022) - 2020
- [c6]Hajime Shibata, Gerry Taylor, Bob Schell, Victor Kozlov, Sharvil Patil, Donald Paterson, Asha Ganesan, Yunzhi Dong, Wenhua Yang, Yue Yin, Zhao Li, Prawal Shrestha, Athreya Gopal, Aathreya S. Bhat
, Shanthi Pavan:
16.6 An 800MHz-BW VCO-Based Continuous-Time Pipelined ADC with Inherent Anti-Aliasing and On-Chip Digital Reconstruction Filter. ISSCC 2020: 260-262
2010 – 2019
- 2019
- [j6]Sharvil Patil
, Suhas Gundu Rao, Yu Chen
, Yannis P. Tsividis
:
Signal Encoding and Processing in Continuous Time Using a Cascade of Digital Delays. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(3): 1017-1030 (2019) - 2018
- [j5]Ning Guo, Yipeng Huang
, Tao Mai, Sharvil Patil, Chi Cao, Mingoo Seok
, Simha Sethumadhavan, Yannis P. Tsividis:
Corrections to "Energy-Efficient Hybrid Analog/Digital Approximate Computation in Continuous Time". IEEE J. Solid State Circuits 53(6): 1870 (2018) - 2017
- [j4]Hajime Shibata
, Victor Kozlov, Zexi Ji, Asha Ganesan, Haiyang Zhu, Donald Paterson, Jialin Zhao, Sharvil Patil, Shanthi Pavan
:
A 9-GS/s 1.125-GHz BW Oversampling Continuous-Time Pipeline ADC Achieving -164-dBFS/Hz NSD. IEEE J. Solid State Circuits 52(12): 3219-3234 (2017) - 2016
- [j3]Sharvil Patil, Alin Ratiu, Dominique Morche, Yannis P. Tsividis:
A 3-10 fJ/conv-step Error-Shaping Alias-Free Continuous-Time ADC. IEEE J. Solid State Circuits 51(4): 908-918 (2016) - [j2]Ning Guo, Yipeng Huang
, Tao Mai, Sharvil Patil, Chi Cao, Mingoo Seok, Simha Sethumadhavan, Yannis P. Tsividis:
Energy-Efficient Hybrid Analog/Digital Approximate Computation in Continuous Time. IEEE J. Solid State Circuits 51(7): 1514-1524 (2016) - [c5]Sharvil Patil, Yannis P. Tsividis:
Digital processing of signals produced by voltage-controlled-oscillator-based continuous-time ADCs. ISCAS 2016: 1046-1049 - 2015
- [j1]Pablo Martínez-Nuevo
, Sharvil Patil, Yannis P. Tsividis:
Derivative Level-Crossing Sampling. IEEE Trans. Circuits Syst. II Express Briefs 62-II(1): 11-15 (2015) - [c4]Ning Guo, Yipeng Huang
, Tao Mai, Sharvil Patil, Chi Cao, Mingoo Seok, Simha Sethumadhavan, Yannis P. Tsividis:
Continuous-time hybrid computation with programmable nonlinearities. ESSCIRC 2015: 279-282 - [c3]Sharvil Patil, Alin Ratiu, Dominique Morche, Yannis P. Tsividis:
A 3-10fJ/conv-step 0.0032mm2 error-shaping alias-free asynchronous ADC. VLSIC 2015: 160-
2000 – 2009
- 2009
- [c2]Ashutosh Mehra, Anu Gupta
, Sharvil Patil, Abhishek Mehra, Subhendu Kumar Sahoo:
A Novel Dynamic Current Boosting Technique for Enhancement of Settling Time and Elimination of Slewing of CMOS Amplifiers. ARTCom 2009: 115-117 - [c1]Amit Agarkhed, Sharvil Patil, Anu Gupta
:
Improved Implementation of CRL and SCRL Gates for Ultra Low Power. ARTCom 2009: 123-125
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last updated on 2024-04-25 05:49 CEST by the dblp team
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