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ORCIDAsuncion Perez-Pascual
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2020 – today
- 2024
[j9]Asun Perez-Pascual
, José Luis Giménez López, Daniel Zapico Palacio, José Marín-Roig:
O-City: Implementation of an Innovative Multimedia Platform for Promoting Orange Economy. ACM Journal on Computing and Cultural Heritage 17(1): 1:1-1:15 (2024)
2010 – 2019
- 2018
- [j8]Asun Perez-Pascual, Alex Hamilton, Robert G. Maunder, Lajos Hanzo:
Conceiving Extrinsic Information Transfer Charts for Stochastic Low-Density Parity-Check Decoders. IEEE Access 6: 55741-55753 (2018) - 2015
- [c13]Jesus Omar Lacruz, Francisco Garcia-Herrero, Ma José Canet, Javier Valls, Asuncion Perez-Pascual:
A 630 Mbps non-binary LDPC decoder for FPGA. ISCAS 2015: 1989-1992 - 2012
- [j7]Fabian Angarita, Trinidad Sansaloni, Asuncion Perez-Pascual, Javier Valls:
Modified Shuffled Based Architecture for High-Throughput Decoding of LDPC Codes. J. Signal Process. Syst. 68(2): 139-149 (2012) - [c12]Fabian Angarita, Vicente Torres-Carot, Asuncion Perez-Pascual, Javier Valls:
High-throughput FPGA-based emulator for structured LDPC codes. ICECS 2012: 404-407 - [c11]Vicente Torres-Carot, Asuncion Perez-Pascual, Trinidad Sansaloni, Javier Valls:
Fully-parallel LUT-based (2048, 1723) LDPC code decoder for FPGA. ICECS 2012: 408-411
2000 – 2009
- 2009
- [j6]Vicente Torres-Carot, A. Perez-Pascual, T. Sansaloni, Javier Valls:
Design and FPGA-Implementation of a High Performance Timing Recovery Loop for Broadband Communications. J. Signal Process. Syst. 56(1): 17-23 (2009) - [j5]A. Perez-Pascual, T. Sansaloni, Vicente Torres-Carot, Vicenc Almenar-Terre, Javier Valls:
Design of Power and Area Efficient Digital Down-converters for Broadband Communications Systems. J. Signal Process. Syst. 56(1): 35-40 (2009) - [c10]Roberto Gutiérrez, Javier Valls, Asuncion Perez-Pascual:
FPGA-implementation of Time-Multiplexed Multiple Constant Multiplication based on carry-save arithmetic. FPL 2009: 609-612 - 2008
- [j4]Fabian Angarita, Ma José Canet, T. Sansaloni, A. Perez-Pascual, Javier Valls:
Efficient Mapping of CORDIC Algorithm for OFDM-Based WLAN. J. Signal Process. Syst. 52(2): 181-191 (2008) - 2007
- [j3]Trinidad Sansaloni, Asuncion Perez-Pascual, Vicente Torres-Carot, Vicenç Almenar, José F. Toledo, Javier Valls:
FFT Spectrum Analyzer Project for Teaching Digital Signal Processing With FPGA Devices. IEEE Trans. Educ. 50(3): 229-235 (2007) - [j2]T. Sansaloni, A. Perez-Pascual, Vicente Torres-Carot, Javier Valls:
Scheme for Reducing the Storage Requirements of FFT Twiddle Factors on FPGAs. J. VLSI Signal Process. 47(2): 183-187 (2007) - [c9]A. Perez-Pascual, T. Sansaloni, Vicente Torres, Vicenç Almenar, Javier Valls:
Design of an efficient digital down-converter for a SDR-based DVB-S receiver. ECCTD 2007: 256-259 - 2006
- [j1]Javier Valls, Trinidad Sansaloni, Asuncion Perez-Pascual, Vicente Torres, Vicenç Almenar:
The use of CORDIC in software defined radios: a tutorial. IEEE Commun. Mag. 44(9): 46-50 (2006) - [c8]Vicente Torres-Carot, A. Perez-Pascual, T. Sansaloni, Javier Valls:
Design of high performance timing recovery loops for communication applications. SiPS 2006: 1-4 - 2005
- [c7]Fabian Angarita, A. Perez-Pascual, T. Sansaloni, Javier Valls:
Efficient FPGA Implementation of CORDIC Algorithm for Circular and Linear Coordinates. FPL 2005: 535-538 - 2003
- [c6]José Marín-Roig, Vicente Torres-Carot, Ma José Canet, Asuncion Perez-Pascual, Trinidad Sansaloni, Francisco Cardells-Tormo, Fabian Angarita, Felip Vicedo, Vicenc Almenar-Terre, Javier Valls-Coquillat:
DIGIMOD: A Tool to Implement FPGA-Based Digital IF and Baseband Modems. FPL 2003: 988-991 - 2002
- [c5]A. Perez-Pascual, T. Sansaloni, Javier Valls:
FPGA-based radix-4 butterflies for HIPERLAN/2. ISCAS (3) 2002: 277-280 - 2001
- [c4]T. Sansaloni, A. Perez-Pascual, Javier Valls:
Distributed arithmetic radix-2 butterflies for FPGA. ICECS 2001: 521-524 - [c3]A. Perez-Pascual, T. Sansaloni, Javier Valls:
FPGA based on-line complex-number multipliers. ICECS 2001: 1481-1484
1990 – 1999
- 1999
- [c2]Marcos Martínez-Peiró, Javier Valls, T. Sansaloni, A. Perez-Pascual, Eduardo I. Boemo:
A comparison between lattice, cascade and direct form FIR filter structures by using a FPGA bit-serial distributed arithmetic implementation. ICECS 1999: 241-244 - [c1]A. Perez-Pascual, Javier Valls, Marcos M. Peiró:
Efficient complex-number multipliers mapped on FPGA. ICECS 1999: 1123-1126
Coauthor Index
aka: Trinidad Sansaloni
aka: Javier Valls
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