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Shi-Ce Ni
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2010 – 2019
- 2019
- [j9]Shijie Li
, Xiaolong Shen
, Yong Dou, Shi-Ce Ni, Jinwei Xu, Ke Yang, Qiang Wang
, Xin Niu:
A Novel Memory-Scheduling Strategy for Large Convolutional Neural Network on Memory-Limited Devices. Comput. Intell. Neurosci. 2019: 4328653:1-4328653:12 (2019) - [c3]Shouyou Song, Zhongru Wang, Shuai Xu, Shi-Ce Ni, Jia Xiao:
A Novel Text Classification Approach Based on Word2vec and TextRank Keyword Extraction. DSC 2019: 536-543 - 2014
- [j8]Shi-Ce Ni, Yong Dou, Dan Zou, Rongchun Li, Qiang Wang
:
Parallel graph traversal for FPGA. IEICE Electron. Express 11(7): 20130987 (2014) - [j7]Xian-Bin Li, Yue-Ke Wang, Jian-Yun Chen, Shi-Ce Ni:
Rapid Acquisition Assisted by Navigation Data for Inter-Satellite Links of Navigation Constellation. IEICE Trans. Commun. 97-B(4): 915-922 (2014) - [j6]Shi-Ce Ni, Yong Dou, Kai Chen
, Jie Zhou:
Design and Implement of High Performance Crypto Coprocessor. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(4): 989-990 (2014) - [j5]Rongchun Li, Yong Dou, Jiaqing Xu, Xin Niu, Shi-Ce Ni:
An Efficient Parallel SOVA-Based Turbo Decoder for Software Defined Radio on GPU. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(5): 1027-1036 (2014) - [c2]Shi-Ce Ni, Yong Dou, Kai Chen
, Lin Deng:
A Novel Design of Flexible Crypto Coprocessor and Its Application. ACA 2014: 128-139 - 2013
- [j4]Dan Zou, Yong Dou, Song Guo, Shi-Ce Ni:
High performance sparse matrix-vector multiplication on FPGA. IEICE Electron. Express 10(17): 20130529 (2013) - [j3]Xiaobao Chen, Zuocheng Xing, Bingcai Sui, Shi-Ce Ni:
Reconfigurable pseudo-NMOS-like logic with hybrid MOS and single-electron transistors. IEICE Electron. Express 10(20): 20130697 (2013) - [c1]Shi-Ce Ni, Yong Dou, Kai Chen
, Lin Deng:
Design and Implementation of Novel Flexible Crypto Coprocessor and Its Application in Security Protocol. NCCET 2013: 61-72 - 2012
- [j2]Rongchun Li, Yong Dou, Yuanwu Lei, Shi-Ce Ni, Song Guo:
Design and Implementation of the Parameterized Multi-Standard High-Throughput Radix-4 Viterbi Decoder on FPGA. IEICE Trans. Commun. 95-B(5): 1602-1611 (2012) - 2010
- [j1]Yong Dou, Jie Zhou, Guiming Wu, Jingfei Jiang, Yuanwu Lei, Shi-Ce Ni:
A Unified Co-Processor Architecture for Matrix Decomposition. J. Comput. Sci. Technol. 25(4): 874-885 (2010)
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